- 19 Jun, 2018 6 commits
-
-
Nishanth Menon authored
Do proper initialization of GIC V3. This will allow CP15 access to GIC from "normal world" (aka HLOS) via mrc/mcr calls. K3 SoC family uses GICv3 compliant GIC500 without compatibility for legacy GICv2. Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Benjamin Fair <b-fair@ti.com> Signed-off-by:
Andrew F. Davis <afd@ti.com>
-
Nishanth Menon authored
Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC clock is selected statically and override option if the platform has a different configuration. Signed-off-by:
-
Nishanth Menon authored
Signed-off-by:
-
Nishanth Menon authored
This library will be used to properly set up mappings from different bootloaders at different exception levels. It ensures that memory mapped devices such as UARTs are still accessible and memory regions have the correct access permissions. Signed-off-by:
-
Benjamin Fair authored
The K3 family of SoCs has multiple interconnects. The key interconnect for high performance processors is the MSMC3 interconnect. This is an io-coherent interconnect which exports multiple ports for each processor cluster. Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated such that the instance of ATF does not manage it. Define macros in platform_def.h to help handle this. Signed-off-by:
-
Nishanth Menon authored
Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by:
-
