- 18 Jan, 2019 2 commits
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Anthony Zhou authored
Main fixes: Add suffix U for constant [Rule 10.1] Match the operands type [Rule 10.4] Use UL replace U for that constant define that need do "~" operation [Rule 12.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch adds the driver for the general purpose DMA hardware block on newer Tegra SoCs. The GPCDMA is a special purpose DMA used to speed up memory copy operations to/from DRAM and TZSRAM. This patch introduces a macro 'USE_GPC_DMA' to allow platforms to override CPU based memory operations. Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 16 Jan, 2019 3 commits
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Krishna Reddy authored
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO) based on the latest info received from HW team as a part of BW issues debug. SMMU Client config register are obsolete from T186. Clean up the unnecessary register definitions and programming of these registers. Cleanup unnecessary macros as well. Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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Varun Wadekar authored
This patch fixes the logic to check if Atomics hardware block is powered on during boot Reported by: Peter De Schrijver <pdeschrijver@nvidia.com> Change-Id: I4a6521bcee37225d1402321151c48fa631776b8a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 14 Jul, 2017 1 commit
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 15 Jun, 2017 3 commits
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Anthony Zhou authored
Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch moves the GPU reset state check, during VideoMem resize, to the common SiP handler, to reduce code duplication. Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch fixes the logic to check if the command written to the MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module. Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 01 May, 2017 1 commit
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Varun Wadekar authored
The video memory carveout has to be re-sized depending on the Video content. This requires the NS world to send us new base/size values. Before setting up the new region, we must zero out the previous memory region, so that the video frames are not leaked to the outside world. This patch adds the logic to zero out the previous memory carveout region. Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 26 Apr, 2017 1 commit
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Varun Wadekar authored
This patch enables the assert in the context save routine by default, for all flavours of the build. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 21 Apr, 2017 1 commit
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Varun Wadekar authored
This patch sanity checks the SMMU context created by the platform code. The first entry contains the size of the array; which the driver now verifies before moving on with the save. This patch also fixes an error in the calculation of the size of the context that gets copied to TZDRAM. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 19 Apr, 2017 1 commit
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Varun Wadekar authored
This patch fixes the size used to save the context, when the device enters System Suspend. Reported by: David Cunado Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 13 Apr, 2017 5 commits
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Varun Wadekar authored
This patch restores the MC_TXN_OVERRIDE settings when we exit from System Suspend. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
During boot, USB3 and flash media (SDMMC/SATA) devices need access to IRAM. Because these clients connect to the MC and do not have a direct path to the IRAM, the MC implements AHB redirection during boot to allow path to IRAM. In this mode, accesses to a programmed memory address aperture are directed to the AHB bus, allowing access to the IRAM. The AHB aperture is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are initialized to disable this aperture. Once bootup is complete, we must program IRAM base/top, thus disabling access to IRAM. This patch provides functionality to disable this access. The tegra port calls this new function before jumping to the non-secure world during cold boot. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch programs MC transaction overrides settings using mc_txn_override_cfgs array for all Tegra chips beyond Tegra186 rev. A01 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 10 Apr, 2017 1 commit
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Varun Wadekar authored
This patch enables the 'xlat_table_v2' library for the Tegra Memory Controller driver. This library allows us to dynamically map/unmap memory regions, with MMU enabled. The Memory Controller driver maps/unmaps non-overlapping Video Memory region, to clean it of any secure contents, before it resizes the region. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 07 Apr, 2017 5 commits
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Pritesh Raithatha authored
This patch empowers the platforms to provide the settings (e.g. stream ID, security setting, transaction overrides) required by the Memory Controller driver. This allows the platforms to program the Memory Controller as per their needs and makes the driver scalable. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch removes the memory controller configuration setting, which allowed non-secure access to the TZSRAM memory. Change-Id: Ic13645ba6a7694f192565962df40ca4fb8130f23 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a config to the memory controller driver to enable SMMU device init during boot. Tegra186 platforms keeps it enabled by default, but future platforms might not support it. Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a new config to enable MC settings for the AFIW and AFIR devices. Platforms must enable this config on their own. Change-Id: I53b450117e4764ea76d9347ee2928f9be178b107 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch moves the smmu driver introduced by the Tegra186 port to tegra/common so that future chips can (re)use it. Change-Id: Ia44c7f2a62fb2d8869db3a44742a8c6b13c49036 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 05 Apr, 2017 4 commits
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Varun Wadekar authored
This patch moves the chip specific memory controller driver defines to the appropriate tegra_def.h files, for future compatibility. Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Mustafa Yigit Bilgen authored
Remove stream ID overrides for AON. AON drives its own stream ID when accesing IOVA memory. However, it needs to use a physical stream ID when accesing GSC memory. Overriding stream ids prevents AON from accessing GSC memory, so remove them to allow AON to access GSCs. Change-Id: Ia2b11014d9780c4546b5e781621ae4cd413735cc Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Vivek Aseeja authored
This patch reverts the APE overrides added for chip verification. Change-Id: Ib85560934d63f6e41e95ef6898a341f24761a517 Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
Save TZDRAM settings for SC7 resume firmware to restore. SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0 SECURITY_BOM_HI: MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1 SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1 Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 30 Mar, 2017 2 commits
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Varun Wadekar authored
This patch switches to the functions which identify the underlying platform in order to calculate the chip SKU. Change-Id: I20cf5623465289ccfab28d6578efcf762bfeb456 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables the configuration settings for the TZRAM aperture by programming the base/size of the aperture and restricting access to it. We allow only the CPU to read/write by programming the access configuration registers to 0. Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Mar, 2017 1 commit
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Varun Wadekar authored
This patch fixes the logic to calculate the higher bits for TZRAM's base/end addresses. Fixes coverity error "31853: Wrong operator used (CONSTANT_EXPRESSION_RESULT)" Change-Id: Iff62ef18cba59cd41ad63a5c71664872728356a8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Mar, 2017 5 commits
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Varun Wadekar authored
This patch fixes the programming logic for the Video memory carveout's size. The Memory Controller expects the size in terms of MBs instead of bytes. Change-Id: Ia8261b737448bae9a435fe21ab336126785d4279 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes stream ID override for the Security Engine hardware block as its stream ID is programmed by the NS world driver. Original change by Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: Ia6523c1a1bb0a82bdeb878feb55670813899bdac Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The Tegra simulation environment has limited capabilities. This patch checks the chip's major and minor versions to decide the features to enable/disable - MCE firmware version checking is disabled and limited Memory Controller settings are enabled Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables overrides for APE domains to allow the chip verification software harness (MODS) to execute its test cases. Original change by Harvey Hsieh <hhsieh@nvidia.com> Change-Id: I09b22376068c5b65d89c2a53154ccb2c60d955bd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch reprograms MSS to make ROC deal with ordering of MC traffic after boot and system suspend exit. This is needed as device boots with MSS having all control but POR wants ROC to deal with the ordering. Performance is expected to improve with ROC but since no one has really tested the performance, keep the option configurable for now by introducing a platform level makefile variable. Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 22 Mar, 2017 1 commit
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Varun Wadekar authored
The memory controller loses its settings when the device enters system suspend state. This patch adds a handler to restore the Video Memory settings in the memory controller, which would be called after exiting the system suspend state. Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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