- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by:Ambroise Vincent <ambroise.vincent@arm.com>
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- 26 Jun, 2019 4 commits
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Hadi Asyrafi authored
Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
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Hadi Asyrafi authored
Signed-off-by: -
Hadi Asyrafi authored
Signed-off-by: -
Hadi Asyrafi authored
Signed-off-by:
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- 21 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by:
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- 13 Mar, 2019 2 commits
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: -
Muhammad Hadi Asyrafi Abdul Halim authored
To support the enablement of QSPI booting Signed-off-by:
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- 08 Mar, 2019 2 commits
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com>
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:
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- 07 Mar, 2019 2 commits
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Muhammad Hadi Asyrafi Abdul Halim authored
Change map region for device 2 from non-secure to secure Signed-off-by: -
Tien Hock, Loh authored
We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by:
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- 26 Feb, 2019 1 commit
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:
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- 13 Feb, 2019 1 commit
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Loh Tien Hock authored
A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by:
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- 04 Feb, 2019 1 commit
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
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