- 10 Jul, 2021 5 commits
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Pali Rohár authored
Armada 3700 uses WTP so use WTP variable directly. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I216b40ffee1f3f8abba4677f050ab376c2224ede
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Pali Rohár authored
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with latest TF-A code base. Marvell do not provide these old tarballs on Extranet anymore. Public version on github repository contains all patches and is working fine, so for public TF-A builds use only public external dependencies from git. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
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Pali Rohár authored
BLE source files depend on external Marvell mv-ddr-marvell tree (specified in $(MV_DDR_PATH) variable) and its header files. Add dependency on $(MV_DDR_LIB) target which checks that variable $(MV_DDR_PATH) is correctly set and ensures that make completes compilation of mv-ddr-marvell tree. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47
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Pali Rohár authored
Do not set all include directories, including those for external targets in one PLAT_INCLUDES variable. Instead split them into variables: * $(PLAT_INCLUDES) for all TF-A BL images * BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image * $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree Include directory $(CURDIR)/drivers/marvell is required by TF-A BL images, so move it from ble.mk to a8k_common.mk. Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so move it into BLE target specific $(PLAT_INCLUDES) variable. And remaining include directories specified in ble.mk are needed only for building external dependences from Marvell mv-ddr tree, so move them into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB) target. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67
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Pali Rohár authored
Target mrvl_flash depends on external mv_ddr source code which is not part of TF-A project. Do not expect that it is pre-downloaded at some specific location and require user to specify correct path to mv_ddr source code via MV_DDR_PATH build option. TF-A code for Armada 37x0 platform also depends on mv_ddr source code and already requires passing correct MV_DDR_PATH build option. So for A8K implement same checks for validity of MV_DDR_PATH option as are already used by TF-A code for Armada 37x0 platform. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
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- 08 Jul, 2021 2 commits
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Abhyuday Godhasara authored
All API calls except non-blocking should wait for IPI response and read buffer to check return status from firmware. Some of API calls are not reading status from IPI payload data. Use sync method which reads actual return status from IPI payload. Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Change-Id: I6f568b85d0da639c264f507122e3015807d8423d
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Abhyuday Godhasara authored
All API calls except non-blocking should wait for IPI response and read buffer to check return status from firmware. Some of API calls are not reading status from IPI payload data. Use sync method which reads actual return status from IPI payload. Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> Change-Id: I78f9c061a80cee6d524ade4ef124ca88ce1848cf
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- 02 Jul, 2021 5 commits
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Edward-JW Yang authored
Support DRAM/MAINPLL/26M off when system suspend. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77
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Edward-JW Yang authored
Add drivers to support MCUSYS off when system suspend. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
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Elly Chiang authored
Add PTP3 drivers to protect CPU excessive voltage drop in CPU heavy loading. Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d Signed-off-by: Elly Chiang <elly.chiang@mediatek.com>
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Tinghan Shen authored
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by read/write the subsys registers. However, the register region of subsys doesn't include in the MMU mapping region. It triggers MMU faults. This patch extends the MMU region 0 size to cover all mt8195 HW modules. This patch also remove MMU region 1 because region 0 covers region 1. Change-Id: I3a186ed71d0d963b59ae55e27a6d27a01fe4f638 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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Daniel Boulby authored
The partition layout description JSON file generated by TF-A tests declares a fourth test partition called Ivy demonstrating the implementation of a S-EL0 partition supported by a S-EL1 shim. Change-Id: If8562acfc045d6496dfdb3df0524b3a069357f8e Signed-off-by: Daniel Boulby <daniel.boulby@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
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- 30 Jun, 2021 2 commits
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Patrick Delaunay authored
Add a generic function to setup the stm32image IO. Change-Id: I0f7cf4a6030605037643f3119b809e0319d926af Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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Yann Gautier authored
Add a panic() at the end of stm32mp_io_setup() if the boot interface given in ROM code boot context is not supported. Change-Id: I0d50f21a11231febd21041b6e63108cc3e6f4f0c Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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- 29 Jun, 2021 2 commits
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Sandrine Bailleux authored
We don't ever expect to load a binary with an STM32 header on the Arm FVP platform so remove this type of image from the list of measurements. Also remove the GPT image type from the list, as it does not get measured. GPT is a container, just like FIP is. We don't measure the FIP but rather the images inside it. It would seem logical to treat GPT the same way. Besides, only images that get loaded through load_auth_image() get measured right now. GPT processing happens before that and is handled in a different way (see partition_init()). Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Manish Pandey authored
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode. The underlying changes for enabling PIE in aarch32 is submitted in commit 4324a14b Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
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- 28 Jun, 2021 2 commits
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Arunachalam Ganapathy authored
Third instance of cactus is a UP SP. Set its vcpu count to 1. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I34b7feb2915e6d335e690e89dea466e75944ed1b
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Arunachalam Ganapathy authored
Change OP-TEE, Cactus SPs UUID to string format Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I32dbf40e4c5aa959bb92d3e853072aea63409ddc
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- 22 Jun, 2021 3 commits
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Yann Gautier authored
In stm32mp1_syscfg_disable_io_compensation(), to disable the IO compensation cell, we have to set the corresponding bit in SYSCFG_CMPENCLRR register, instead of clearing the bit in SETR register. Change-Id: I510a50451f8afb9e98c24e1ea84efbf73a39e6b4 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The dependency on this macro was added by patch [1]. But the macro itself was forgotten in the patch. [1] 128e0b3e ("stm32mp1: update rules for stm32image tool") Change-Id: I49219e1e13828b97b95f404983da33ef4567fe23 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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Nicolas Le Bayon authored
BSEC services should return SMC error codes as other IDs (defined in stm32mp1_smc.h) and not BSEC driver ones. So that non-secure caller is able to treat them correctly. In global SMC handler, unknown ID should also return a value from this definition list, and not the generic one, which seems not well adapted for our needs. Two unsigned values initializations are also changed from 0 to 0U. Change-Id: Ib6fd3866a748cefad1d13d48f7be38241621023e Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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- 17 Jun, 2021 2 commits
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Venkatesh Yadav Abbarapu authored
As there is constraint with the space for the release builds, remove some of the legacy code. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852
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Igor Opaniuk authored
Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides architectural reset definitions and vendor-specific resets. By default warm reset is triggered. Also refactor existing implementation of wdog reset, add details about each flag used. Change-Id: Ia7348c32c385f1c61f8085776e81dd1e38ddda5c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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- 15 Jun, 2021 5 commits
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Jiafei Pan authored
Add macro of SUPPORTED_BOOT_MODE for board lx2160ardb, lx2160aqds, lx2162aqds. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I4451ca030eca79c9bc5fee928eec497a7f0e878c
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Jiafei Pan authored
1. Added the build macro "add_boot_mode_define". 2. Use the macro to validate current BOOT_MODE against the pre-determined list of SUPPORTED_BOOT_MODE, so each platform need to define the list: SUPPORTED_BOOT_MODE. 3. Reports error if BOOT_MODE is not in SUPPORTED_BOOT_MODE list, or BOOT_MODE is not supported yet althoug it is in SUPPORTED_BOOT_MODE. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I29be60ecdb19fbec1cd162e327cdfb30ba629b07
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Jiafei Pan authored
Move some soc make variables to new soc_common_def.mk, then it can be reused by other platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ia30bd332c95b6475f1cfee2f03a8ed3892a9568d
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Jiafei Pan authored
Use common code in common file to configure platform. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I72fe22751f12b8a4996a7b9f75fae4c912ea86de
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Jiafei Pan authored
Move some common make variables to new plat_common_def.mk, then it can be reused by other platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I37bd65b0f8124f63074fa03339f886c2cdb30bd3
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- 14 Jun, 2021 1 commit
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Michal Simek authored
In case of TF-A running out of DDR there is a need to reserved memory to let other SW know that none can't use this memory. HW wise this region can be (and should be) also protected by protection unit XMPU. This is the first step to add reserved memory location to DT. DT address corresponds with default address in U-Boot and also default address in Xilinx BSPs. Code is valid only when TF-A runs out of DDR. When it runs out of OCM there is no need to reseve anything because OCM is hidden to OS. Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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- 12 Jun, 2021 2 commits
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Peng Fan authored
Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor could use SDEI to do hypervisor management, after physical IRQ has been disabled routing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I8308c629448bd8adca9d3d25701adcf0c5a6afc2
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Peng Fan authored
Add sdei support for i.MX8MN, this is to let jailhouse Hypervisor could use SDEI to do hypervisor management, after physical IRQ has been disabled routing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ie15fffdd09e1bba1b22334b8ccac2335c96b8b4d
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- 04 Jun, 2021 3 commits
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Yann Gautier authored
Device Tree address is now a parameter for dt_open_and_check() function. This will allow better flexibility when introducing PIE and FIP. The fdt pointer is now only assigned if the given address holds a valid device tree file. This allows removing the fdt_checked variable, as we now check fdt is not null. Change-Id: I04cbb2fc05c9c711ae1c77d56368dbeb6dd4b01a Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The boot device is now checked inside a dedicated rule, that is only called during BL2 compilation step Change-Id: Ie7bcd1f166285224b0c042238989a82f7b6105c6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Vyacheslav Yurkov authored
Added a new STM32MP_EMMC_BOOT option, which is used to look for SSBL in the same eMMC boot partition TF-A booted from at a fixed 256k offset. In case STM32 image header is not found, the boot process rolls back to a GPT partition look-up scheme. Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: I85a87dc9ae7f2b915ed8e584be80f4b3588efc48
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- 03 Jun, 2021 5 commits
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Jan Kiszka authored
Add basic SDEI support, implementing the software event 0 only for now. This already allows hypervisors like Jailhouse to use SDEI for internal signaling while passing the GICC through to the guest (see also IMX8). With SDEI on, we overrun the SRAM and need to stay in DRAM. So keep SDEI off by default. Co-developed-by: Angelo Ruocco <angeloruocco90@gmail.com> Signed-off-by: Angelo Ruocco <angeloruocco90@gmail.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: Ic0d71b4ef0978c0a34393f4e3530ed1e24a39ca2
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Yann Gautier authored
The io_dummy code and function calls are only used in case BL32 is TF-A SP_min, and not OP-TEE. This code in bl2_io_storage can then be put under #ifndef AARCH32_SP_OPTEE. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I52787a775160b335f97547203f653419621f5147
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Yann Gautier authored
STM32MP1 does not use BL1, the loading of BL2 is done by ROM code. It is then useless to have an entry BL2_IMAGE_ID in the policies. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I464cedf588114d60522433123f8dbef32ae36818
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Yann Gautier authored
OPTEE_PAGER defines are renamed OPTEE_CORE. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I4c28d3b0a6ed843088a3ef06e3e348ce689fabde
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Olivier Deprez authored
Fix a remainder from early prototyping. OP-TEE as a secure partition does not need specific SMC function id pass through to EL3. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I2843d1b9a5eb4c966f82790e1655fb569c2de7d4
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- 02 Jun, 2021 1 commit
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Yann Gautier authored
The UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined in include/tools_share/firmware_image_package.h for BL32_EXTRA1 and TRUSTED_KEY_CERT. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I517f8f9311585931f2cb931e0588414da449b694
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