- 26 Jul, 2017 5 commits
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Sandrine Bailleux authored
When using __builtin_ctzll() in AArch32 code, the compiler may translate that into a call to the __ctzdi2() function. In this case, the linking phase fails because TF doesn't provide an implementation for it. This patch imports the implementation of the __ctzdi2() function from LLVM's compiler-rt project and hooks it into TF's build system. The ctzdi2.c file is an unmodified copy from the master branch as of July 19 2017 (SVN revision: 308480). Change-Id: I96766a025ba28e1afc6ef6a5c4ef91d85fc8f32b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Previous patches have made it possible to specify the physical and virtual address spaces sizes for each translation context. However, there are still some places in the code where the physical (resp. virtual) address space size is assumed to be PLAT_PHY_ADDR_SPACE_SIZE (resp. PLAT_VIRT_ADDR_SPACE_SIZE). This patch removes them and reads the relevant address space size from the translation context itself instead. This information is now passed in argument to the enable_mmu_arch() function, which needs it to configure the TCR_ELx.T0SZ field (in AArch64) or the TTBCR.T0SZ field (in AArch32) appropriately. Change-Id: I20b0e68b03a143e998695d42911d9954328a06aa Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
This patch refactors both the AArch32 and AArch64 versions of the function enable_mmu_arch(). In both versions, the code now computes the VMSA-related system registers upfront then program them in one go (rather than interleaving the 2). In the AArch64 version, this allows to reduce the amount of code generated by the C preprocessor and limits it to the actual differences between EL1 and EL3. In the AArch32 version, this patch also removes the function enable_mmu_internal_secure() and moves its code directly inside enable_mmu_arch(), as it was its only caller. Change-Id: I35c09b6db4404916cbb2e2fd3fda2ad59f935954 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
In both the AArch32 and AArch64 versions, this function used to check the sanity of the PLAT_PHY_ADDR_SPACE_SIZE in regard to the architectural maximum value. Instead, export the xlat_arch_get_max_supported_pa() function and move the debug assertion in AArch-agnostic code. The AArch64 used to also precalculate the TCR.PS field value, based on the size of the physical address space. This is now done directly by enable_mmu_arch(), which now receives the physical address space size in argument. Change-Id: Ie77ea92eb06db586f28784fdb479c6e27dd1acc1 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
In a previous patch, the xlat_ctx_t type has been made public. This patch now makes the *_ctx() APIs public. Each API now has a *_ctx() variant. Most of them were already implemented and this patch just makes them public. However, some of them were missing so this patch introduces them. Now that all these APIs are public, there's no good reason for splitting them accross 2 files (xlat_tables_internal.c and xlat_tables_common.c). Therefore, this patch moves all code into xlat_tables_internal.c and removes xlat_tables_common.c. It removes it from the library's makefile as well. This last change introduces a compatibility break for platform ports that specifically include the xlat_tables_common.c file instead of including the library's Makefile. The UniPhier platform makefile has been updated to now omit this file from the list of source files. The prototype of mmap_add_region_ctx() has been slightly changed. The mmap_region_t passed in argument needs to be constant because it gets called from map_add(), which receives a constant region. The former implementation of mmap_add() used to cast the const qualifier away, which is not a good practice. Also remove init_xlation_table(), which was a sub-function of init_xlat_tables(). Now there's just init_xlat_tables() (and init_xlat_tables_ctx()). Both names were too similar, which was confusing. Besides, now that all the code is in a single file, it's no longer needed to have 2 functions for that. Change-Id: I4ed88c68e44561c3902fbebb89cb197279c5293b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 25 Jul, 2017 4 commits
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Sandrine Bailleux authored
At the moment, the translation context type (xlat_ctx_t) is a private type reserved for the internal usage of the translation table library. All exported APIs (implemented in xlat_tables_common.c) are wrappers over the internal implementations that use such a translation context. These wrappers unconditionally pass the current translation context representing the memory mappings of the executing BL image. This means that the caller has no control over which translation context the library functions act on. As a first step to make this code more flexible, this patch exports the 'xlat_ctx_t' type. Note that, although the declaration of this type is now public, its definition stays private. A macro is introduced to statically allocate and initialize such a translation context. The library now internally uses this macro to allocate the default translation context for the running BL image. Change-Id: Icece1cde4813fac19452c782b682c758142b1489 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Move the header files that provide translation tables architectural definitions from the library v2 source files to the library include directory. This allows to share these definitions between both versions (v1 and v2) of the library. Create a new header file that includes the AArch32 or AArch64 definitions based on the AARCH32 build flag, so that the library user doesn't have to worry about handling it on their side. Also repurpose some of the definitions the header files provide to concentrate on the things that differ between AArch32 and AArch64. As a result they now contain the following information: - the first table level that allows block descriptors; - the architectural limits of the virtual address space; - the initial lookup level to cover the entire address space. Additionally, move the XLAT_TABLE_LEVEL_MIN macro from xlat_tables_defs.h to the AArch32/AArch64 architectural definitions. This new organisation eliminates duplicated information in the AArch32 and AArch64 versions. It also decouples these architectural files from any platform-specific information. Previously, they were dependent on the address space size, which is platform-specific. Finally, for the v2 of the library, move the compatibility code for ADDR_SPACE_SIZE into a C file as it is not needed outside of this file. For v1, this code hasn't been changed and stays in a header file because it's needed by several files. Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
The DEVICE2 memory range is needed to access the Root of Trust Public Key registers. This is not needed when Trusted Board Boot is disabled so it's safer to not map it in this case. This also saves one level-2 page table in each of BL1 and BL2 images. Also add some comments. Change-Id: I67456b44f3fd5e145f6510a8499b7fdf720a7273 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
This patch adds some debug prints to display some statistics about page tables usage. They are printed only if the LOG_LEVEL is at least 50 (i.e. VERBOSE). Sample output for BL1: VERBOSE: Translation tables state: VERBOSE: Max allowed PA: 0xffffffff VERBOSE: Max allowed VA: 0xffffffff VERBOSE: Max mapped PA: 0x7fffffff VERBOSE: Max mapped VA: 0x7fffffff VERBOSE: Initial lookup level: 1 VERBOSE: Entries @initial lookup level: 4 VERBOSE: Used 4 sub-tables out of 5 (spare: 1) Change-Id: If38956902e9616cdcd6065ecd140fe21482597ea Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 20 Jul, 2017 1 commit
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davidcunado-arm authored
Fix order of includes
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- 14 Jul, 2017 6 commits
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davidcunado-arm authored
Poplar: Initial commit for Poplar E-96Boards
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davidcunado-arm authored
hikey: Add BL32 (OP-TEE) support v2
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Jorge Ramirez-Ortiz authored
The board features the Hi3798C V200 with an integrated quad-core 64-bit ARM Cortex A53 processor and high performance Mali T720 GPU, making it capable of running any commercial set-top solution based on Linux or Android. Its high performance specification also supports a premium user experience with up to H.265 HEVC decoding of 4K video at 60 frames per second. SOC Hisilicon Hi3798CV200 CPU Quad-core ARM Cortex-A53 64 bit DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB USB Two USB 2.0 ports One USB 3.0 ports CONSOLE USB-micro port for console support ETHERNET 1 GBe Ethernet PCIE One PCIe 2.0 interfaces JTAG 8-Pin JTAG EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor WIFI 802.11AC 2*2 with Bluetooth CONNECTORS One connector for Smart Card One connector for TSI The platform boot sequence is as follows: l-loader --> arm_trusted_firmware --> u-boot Repositories: - https://github.com/Linaro/poplar-l-loader.git - https://github.com/Linaro/poplar-u-boot.git U-Boot is also upstream in the project's master branch. Make sure you are using the correct branch on each one of these repositories. The definition of "correct" might change over time (at this moment in time this would be the "latest" branch). Build Line: make CROSS_COMPILE=aarch64-linux-gnu- all fip SPD=none DEBUG=1 PLAT=poplar BL33=/path/to/u-boot.bin Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Alex Elder <elder@linaro.org> Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Alex Elder <elder@linaro.org>
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davidcunado-arm authored
hikey960 updates
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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Isla Mitchell authored
This fix modifies the order of #includes in ARM standard platforms to meet the ARM TF coding standard. Change-Id: Ide19aad6233babda4eea2d17d49e523645fed1b2 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 12 Jul, 2017 8 commits
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions in order to retain header groupings, minimise changes to imported headers, and where there are headers within the #if and #ifndef statements. Change-Id: I65085a142ba6a83792b26efb47df1329153f1624 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
PLATFORM_LINKER_FORMAT and PLATFORM_LINKER_ARCH defines are removed from plat/hisilicon/hikey/include/platform_def.h since there are already defined in include/plat/common/common_def.h which is included by plat/hisilicon/hikey/hikey_def.h which is included by plat/hisilicon/hikey/include/platform_def.h The line $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) is removed from plat/hisilicon/hikey/platform.mk to clear the warning below: Makefile:544: warning: overriding commands for target `check_SCP_BL2' plat/hisilicon/hikey/platform.mk:19: warning: ignoring old commands for target `check_SCP_BL2' $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) already exists in Makefile and applies to plat hikey so is redundant in plat/hisilicon/hikey/platform.mk Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
The line $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) is removed from plat/hisilicon/hikey960/platform.mk to clear the warning below: Makefile:544: warning: overriding commands for target `check_SCP_BL2' plat/hisilicon/hikey960/platform.mk:13: warning: ignoring old commands for target `check_SCP_BL2' $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) already exists in Makefile and applies to plat hikey960 so is redundant in plat/hisilicon/hikey960/platform.mk Signed-off-by: Victor Chong <victor.chong@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 11 Jul, 2017 1 commit
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Victor Chong authored
Fix cortex a53 errata issues: #836870, #843419, #855873. Signed-off-by: Victor Chong <victor.chong@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 10 Jul, 2017 4 commits
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davidcunado-arm authored
zynqmp: Remove duplicate 'const' declaration
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davidcunado-arm authored
rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume
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davidcunado-arm authored
rockchip: support to use hdcp for rk3399
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Haojian Zhuang authored
Fix cortex a53 errata issues: #836870, #843419, #855873. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 07 Jul, 2017 3 commits
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davidcunado-arm authored
Release v1.4: Update minor version number to 4
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davidcunado-arm authored
Updates user guide following out of box testing.
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Eleanor Bonnici authored
Change-Id: I0cd355d9fc7f14fb4eabb443d596d6f0858f609e Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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- 06 Jul, 2017 7 commits
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davidcunado-arm authored
Update readme for v1.4 release
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David Cunado authored
Change-Id: I8676a22649dce92d0ddd98013fc6dafcfbe94c90 Signed-off-by: David Cunado <david.cunado@arm.com>
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davidcunado-arm authored
Release v1.4: update change-log.rst
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David Cunado authored
Updated change-log.rst with summary of changes since release v1.3. Change-Id: Iecd31ed315bd9ad7ffe8bce6550f7c90e1e3a9b0 Signed-off-by: David Cunado <david.cunado@arm.com>
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davidcunado-arm authored
Migrate to Linaro release 17.04
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David Cunado authored
ARM TF has been tested against Linaro Release 17.04 - the Linaro binaries have been update and also the version of the compiler. Linaro binaries: 17.01 --> 17.04 AArch64 & AArch32 compilers: 5.3-2015.05 (gcc 5.3) -> 6.2-2016.11 (gcc 6.2) This patch updates the User Guide is to state that Linaro release 17.04 is supported. Additionally, the following fixes are made to the User Guide: - Removed out of date reference to Linaro release 16.06. - Updated the Juno variant coverage to include r2. Change-Id: Iebbced3356f8c6b3c2bff2df62574db9f937ca7b Signed-off-by: David Cunado <david.cunado@arm.com>
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davidcunado-arm authored
Update Foundation, AEM and Cortex Models versions
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- 05 Jul, 2017 1 commit
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Dan Handley authored
Update the release notes (readme.rst) for the ARM Trusted Firmware v1.4 release. Also, reorder and fix some of the links following the conversion to reStructured text format. Change-Id: I8f5e8aa86cb891f61b6b62cf9fab0ad0f0ebb36b Signed-off-by: Dan Handley <dan.handley@arm.com>
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