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plat/arm: Save BL2 descriptors to reserved memory.

spd: trusty: trusty_setup should bail on unknown image

Add more SIP runtime service for i.MX8

ti: k3: common: Add support for runtime detection of GICR base address

Enable necessary A53 erratas for i.MX8QM and i.MX8MQ

Tf2.0 tegra downstream rebase 1.22.19

When an unknown Trusty image is found, there's no point of still trying
to register the BL32 init handler. Instead, we just should bail out of
the trusty_setup() and allow the system to continue to boot.
Signed-off-by: David Lin <dtwlin@google.com>

NXP's i.MX8QM uses Cortex-A53 r0p4, enable necessary
erratas for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

NXP's i.MX8MQ uses Cortex-A53 r0p4, enable necessary
erratas for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

This patch removes this unused config option from the Tegra186
platform makefiles.

Change-Id: Idcdf6854332a26599323a247289c2d3ce19f475f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the usage of this platform config, as it is always
enabled by all the supported platforms.

Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a platform setup handler that gets called after
the MMU is enabled. Platforms wanting to make use of this handler
should declare 'plat_late_platform_setup' handler in their platform
files, to override the default weakly defined handler.

Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c
Signed-off-by: Dilan Lee <dilee@nvidia.com>

There are Tegra platforms which have limited UART ports and so
all the components have to share the console. The SPE helps out
by collecting all the logs in such cases and prints them on the
shared UART port.

This patch adds a driver to communicate with the SPE driver, which
in turn provides the console.

Change-Id: Ie750520b936b8bed0ab1d876f03fc0a3490a85a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.

Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF.
This patch changes the search criteria, to look for this marker, to
calculate the size of the saved context.

Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.

Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra186 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch returns error if BPMP initialization fails. The platform
code marks the cluster as "runnning" since we wont be able to get
it into the low power state without BPMP.

Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: Steven Kao <skao@nvidia.com>

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.

Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the following MISRA violations:

Rule 8.6: Externally-linked object or function has "no" definition(s).
Rule 11.1: A cast shall not convert a pointer to a function to
any other type.

Change-Id: Ic1f6fc14c744e54ff782c6987dab9c9430410f5e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.

Reported by: Rohit Khanna <rokhanna@nvidia.com>

Change-Id: Ia73ccf04bd246403de4ffff6e5c99e3b00fb98ca
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

MISRA Rule 8.4, A compatible declaration shall be visible when an
object or function with external linkage is defined.

This patch adds static for local array to fix this defect.

Change-Id: I8231448bf1bc0b1e59611d7645ca983b83d5c8e3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.

MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).

This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.

The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.

1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
   BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
   0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
   non zero.

The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.

Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch calls the 'early_init' handler earlier during boot. This
allows the platforms using Tegra186 onwards to init the BPMP interface
earlier.

Change-Id: I0d540df39de7864ce9051ebe11eca5432c462ebf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Main Fixes:

Use int32_t replace int [Rule 4.6]

Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]

Force operands of an operator to the same type category [Rule 10.4]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I98caa330c371757eb2dfb9438448cb99115ed907
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: Steven Kao <skao@nvidia.com>

MISRA Rule 21.6, The standard library input/output functions
shall not be used.

This patch removes headers that are not really needed.

Change-Id: I746138ce7ee95d7ca985d020f89b2738d997a7a2
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.

Change-Id: Id76175c2a7d931227589468511365599e2908411
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

This patch enables the '-nostdlib' flag to instruct the compiler
to not use the standard system libraries and startup files.

Change-Id: Ibf34856f7579ed686280cee19c35d08448cf921c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch corrects the logic to read the uncore command/response bits
from the command/response values. The previous logic tapped into incorrect
bits leading to garbage counter values.

Change-Id: Ib8327ca3cb3d2086bb268e9a5366865cdf35b493
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch modifies the timeout loop to use udelay() instead of
mdelay(). This helps with the boot time on some platforms which
issue a lot of MCE calls and every mdelay adds up increasing the
boot time by a lot.

Change-Id: Ic50081b73e1cbc2714361235b5c396e294b8f752
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

MISRA Rule 8.3, All declarations of an object or function
shall use the same names and type qualifiers.

This patch removes unused function(s).

Change-Id: I90865c003d46f1dc08bfb5f4fe8a327ea42a2bb7
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch provides helper function to read the ID_AFR0_EL1
system register for platforms.

Change-Id: Id5491b18e3bf9f619d98d6cc8efd9d2cf5918c9d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory
descriptors describing the list of executable images are created in BL2
R/W memory, which could be possibly corrupted later on by BL31/BL32 due
to overlay. This patch creates a reserved location in SRAM for these
descriptors and are copied over by BL2 before handing over to next BL
image.

Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR
is enabled.

Fixes ARM-Software/tf-issues#626

Change-Id: I755735706fa702024b4032f51ed4895b3687377f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

Integration+linaro warp7 tbb

Valid addresses for GICR base are always a set calculable distance from
the GICD and is based on the number of cores a given instance of GICv3 IP
can support. The formula for the number of address bits is given by the
ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to
one for GICR instances. Holes in the GIC address space are also
guaranteed to safely return 0 on reads. This allows us to support runtime
detection of the GICR base address by starting from GIC base address plus
BIT(18) and walking until the GICR ID register (IIDR) is detected. We
stop searching after BIT(20) to prevent searching out into space if
something goes wrong. This can be extended out if we ever have a device
with 16 or more cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>

TI K3 Clear proxy receive queue on transmit