- 07 Jun, 2017 2 commits
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Haojian Zhuang authored
BL2 loads MCU firmware & BL31 on hikey960 platform. The MCU firmware is used to implement low power feature. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Support BL1 on HiKey960 platform. When recovery mode is detected, BL1 loads NS BL1U that flushs images into UFS. When normal boot mode is detected, BL1 loads BL2. Fix for https://github.com/ARM-software/tf-issues/issues/486 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 31 May, 2017 4 commits
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Leo Yan authored
This patch is to enable CPU suspend/resume and system level's suspend/resume; also enable system power off state. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Leo Yan authored
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port for cluster 0 in BL31 platform setup flow. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Leo Yan authored
Fix for CPU topology so present the CPU core numbers for two clusters; Base on this fixing, the PSCI can maintain correct power states. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Fix uninitliazed variable in ddr driver code. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 24 May, 2017 3 commits
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Haojian Zhuang authored
Support BL31 and PSCI. Enable multiple cores in PSCI. Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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Haojian Zhuang authored
BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2 is the mcu firmware that is used to scale cpu frequency and switch low power mode. Change-Id: I1621aa65bea989fd125ee8502fd56ef72362bf97 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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Haojian Zhuang authored
Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1. So BL2 will be loaded from eMMC into SRAM later. Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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