- 02 Jul, 2019 10 commits
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lauwal01 authored
Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by:Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by:
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lauwal01 authored
Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by:
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- 20 Jun, 2019 4 commits
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John Tsichritzis authored
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John Tsichritzis authored
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Ambroise Vincent authored
The previous implementation could behave incorrectly because of the sign extension of the char when compared to the int. Change-Id: I397838b0ec87a6f1af6972d022a8c19a5184b447 Signed-off-by:Ambroise Vincent <ambroise.vincent@arm.com>
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Soby Mathew authored
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- 19 Jun, 2019 1 commit
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John Tsichritzis authored
* changes: fdts: stm32mp1: realign device tree files with internal devs stm32mp1: increase device tree size to 20kB stm32mp1: make dt_get_stdout_node_offset() static stm32mp1: use unsigned values for SDMMC defines stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCES stm32mp1: update doc for U-Boot compilation stm32mp1: add general SYSCFG management stm32mp1: move stm32_get_gpio_bank_clock() to private file clk: stm32mp1: correctly handle Clock Spreading Generator clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array clk: stm32mp1: move oscillator functions to generic file arch: add some defines for generic timer registers
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- 17 Jun, 2019 25 commits
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John Tsichritzis authored
* changes: rcar_gen3: drivers: qos: Move QoS drivers out of staging rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table rcar_gen3: drivers: qos: Fix checkpatch issues rcar_gen3: drivers: qos: V3M: Drop useless comments rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file rcar_gen3: drivers: qos: V3M: Use common register definition rcar_gen3: drivers: qos: E3: Drop extra level of nesting rcar_gen3: drivers: qos: E3: Use common register definition rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros rcar_gen3: drivers: qos: D3: Drop MD pin check rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting() rcar_gen3: drivers: qos: D3: Drop useless comments rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: D3: Use common register definition rcar_gen3: drivers: qos: M3N: Fix checkpatch issues rcar_gen3: drivers: qos: M3N: Drop MD pin check rcar_gen3: drivers: qos: M3N: Drop useless comments rcar_gen3: drivers: qos: M3N: Drop extra level of nesting rcar_gen3: drivers: qos: M3N: Use common register definition rcar_gen3: drivers: qos: M3W: Fix checkpatch issues rcar_gen3: drivers: qos: M3W: Drop MD pin check rcar_gen3: drivers: qos: M3W: Drop useless comments rcar_gen3: drivers: qos: M3W: Drop extra level of nesting rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file rcar_gen3: drivers: qos: M3W: Use common register definition rcar_gen3: drivers: qos: H3: Fix checkpatch issues rcar_gen3: drivers: qos: H3: Drop MD pin check rcar_gen3: drivers: qos: H3: Drop useless comments rcar_gen3: drivers: qos: H3: Drop extra level of nesting rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: H3: Use common register definition rcar_gen3: console: Convert to multi-console API
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Marek Vasut authored
Now that QoS drivers are cleaned up , move them out of staging. Signed-off-by:Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If61ab2157c30b8f5a6b91d2c56ddbb9098ef99e8
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Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
The DBSC QoS settings can be programmed by iterating over a table with register-value pairs and writing those to the registers, add function to do just that. Subsequent patches will convert the DBSC QoS setting functions for each SoC to this new function. Signed-off-by: -
Marek Vasut authored
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
Convert the mstat table from a complex structure to simple sequence of uint64_t values, since the structure described just that and the loop can operate over incrementing sequence of addresses just fine. Signed-off-by: -
Marek Vasut authored
Pull out the mstat fix array into separate file, to align the structure of the driver with the other SoCs. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the V3M QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by: -
Marek Vasut authored
The extra level of nesting is not necessary, drop it. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the E3 QoS init. No functional change. Signed-off-by: -
Marek Vasut authored
Replace the remaining ad-hoc register addresses with proper macros. Signed-off-by: -
Marek Vasut authored
The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: -
Marek Vasut authored
Move the DBSC write enabling and disabling to dbsc_setting() function, to make it local, instead of having it all over the code. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
Convert the mstat table from a complex structure to simple sequence of uint64_t values, since the structure described just that and the loop can operate over incrementing sequence of addresses just fine. Signed-off-by: -
Marek Vasut authored
Pull out the mstat fix array into separate file, to align the structure of the driver with the other SoCs. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the D3 QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by: -
Marek Vasut authored
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: -
Marek Vasut authored
The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by:
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