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Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm reset when using U-Boot SPL as first
stage boot loader.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a

* changes:
  plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k
  plat: marvell: armada: Fix including plat/marvell/marvell.mk file
  plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it

* changes:
  plat: tc0: Configure TZC with secure world regions
  plat: tc0: Enable SPMC execution at S-EL2
  plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
  plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled
  plat: tc0: Disable SPE

* changes:
  lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
  lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
  lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context

The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.

The aem_generic is also not used with qemu_sbsa, in
fact, the platform currently only properly supports
the cortex-a57 cpu.

Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>

Currently a3k target is misusing ${DOIMAGETOOL} target for building flash
and UART images. It is not used for building image tool.

So move ${DOIMAGETOOL} target from common marvell include file into a8k
include file and add correct invocation of ${MAKE} into a3k for building
flash and UART images.

Part of this change is also checks that MV_DDR_PATH for a3k was specified
by user as this option is required for building a3k flash and UART images.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6

This includes configuration for SPMC and trusted OS.

Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3
Signed-off-by: Usama Arif <usama.arif@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

This patch enables SPMC execution at S-EL2 by adding below changes

    - Map TC0_MAP_TZC_DRAM1 for loading SPMC
    - Add details of cactus test secure partitions
    - Adds tc0 spmc manifest file with details on secure partitions
    - Inlcude TOS_FW_CONFIG when SPM is spmd
    - Increases bl2 image size

SPMC at S-EL2 is only enabled when build with SPD=spmd.

Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

To support platforms without Trusted DRAM this patch defines
PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or
DRAM region behind TZC.

Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

Statistical Profiling Extension is not supported by Matterhorn core

Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

Include EL2 registers related to SPE in EL2 context save/restore
routines if architecture supports it and platform wants to use these
features in Secure world.

Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.

Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

AArch64-only platforms do not implement AArch32 at EL1 and higher ELs.
In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0.
So don't save/restore aarch32 system registers in el2_sysregs_context
save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0.

Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

Include file plat/marvell/marvell.mk for platform A3700 was included two
times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and
second time from common file plat/marvell/armada/common/marvell_common.mk.

It caused following warning every time was make called:

    plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean'
    plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean'

Change in this commit removes inclusion of plat/marvell/marvell.mk file in
common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform
needs this include file, add it also into a80x0 platform specific include
file lat/marvell/armada/a8k/common/a8k_common.mk.

Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file
plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global
plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL
are already defined, but it defines MARVELL_SECURE_BOOT variable which is
needed by plat/marvell/armada/a3k/common/a3700_common.mk.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa

* changes:
  plat:qti Mandate SMC implementaion and bug fix
  Update in coreboot_get_memory_type API to include size as well

There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the document.

Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Updated tentative code freeze and release target date
for v2.5 release.

Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Updated code freeze and release information date for v2.4
release.

Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

* changes:
  bl32: add an assert on BL32_SIZE in sp_min.ld.S
  bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S

implementation of SMC call SMCCC_ARCH_SOC_ID
adding debugging logs in mem assign call.
Checking range of param in mem_assign call is from CB_MEM_RAM
or CB_MEM_RESERVED.

Change-Id: Iba51bff154df01e02dcb7715582ffaff7beba26e
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>

Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>

plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it

Some of targets (e.g. mrvl_flash) depends on WTP build option. Other
targets (e.g. fip) can be build also without WTP build option as they do
not depend on it.

This change put all A3720 variables and targets which depends on WTP into
conditional if-endif section, so they are not defined when user has not
supplied WTP build option.

Target mrvl_flash is defined also when WTP was not specified and in this
case it just print error message to help user.

Variables which do not depend on WTP are moved to the top of
a3700_common.mk file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Idb3892233586a0afca3e0e6564279641d2e4b960

Without this node, the board fails to boot and panics in the function
stm32mp_init_auth().

Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The board information values, read in an OTP are never negative,
%u is then used instead of %d.

Change-Id: I3bc22401fb4d54666ddf56411f75b79aca738492
Signed-off-by: Yann Gautier <yann.gautier@st.com>

* changes:
  docs: update STM32MP1 with versions details
  stm32mp1: get peripheral base address from a define
  stm32mp1: add finished good variant in board identifier

* changes:
  drivers: stm32_fmc2_nand: fix boundary check for chip select
  drivers: stm32_fmc2_nand: move to new bindings