- 20 Mar, 2017 3 commits
-
-
Varun Wadekar authored
This patch fixes the incorrect override settings for the SCE hardware block. Original change by Pekka Pessi <ppessi@nvidia.com> Change-Id: I33db55d6004331988b52ca70157aab1409f4829f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch programs the Memory controller's control registers to disable non-secure accesses to the TZRAM. In case these registers are already programmed by the BL2/BL30, then the driver just bails out. Change-Id: Ia1416988050e3d067296373060c717a260499122 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch adds driver for the Memory Controller (v2) in the newer Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of the proprietary block in the past. Change-Id: I78359da780dc840213b6e99954e45e34428d4fff Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-