- 04 Feb, 2021 1 commit
-
-
Yann Gautier authored
In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is wrong. This field is from bit 16 to 23. Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88 Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 20 Jan, 2021 1 commit
-
-
Peng Fan authored
Make the scmi-msg driver reused by others. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124
-
- 13 Oct, 2020 1 commit
-
-
Yann Gautier authored
Retrieve peripheral base address from a define instead of parsing the device tree. The goal is to improve execution time. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b
-
- 24 Sep, 2020 1 commit
-
-
Yann Gautier authored
Depending on compiler, the issue about bool or uint*_t not defined can appear. Correct this by adding stdbool.h and stdint.h includes in etzpc.h. Change-Id: If1419dc511efbe682459fa4a776481fa52a38aa3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 08 Jul, 2020 1 commit
-
-
Etienne Carriere authored
Introduce stm32mp1_register_clock_parents_secure() in stm32mp1 clock driver to allow platform shared resources to register as secure the parent clocks of a clock registered as secure. Change-Id: I53a9ab6aa78ee840ededce67e7b12a84e08ee843 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-
- 17 Jun, 2020 4 commits
-
-
Etienne Carriere authored
This change implements SCMI channels for reading a SCMI message from a shared memory and call the SCMI message drivers to route the message to the target platform services. SMT refers to the shared memory management protocol which is used to get/put message/response in shared memory. SMT is a 28byte header stating shared memory state and exchanged protocol data. The processing entry for a SCMI message can be a secure interrupt or fastcall SMCCC invocation. SMT description in this implementation is based on the OP-TEE project [1] itself based in the SCP-firmware implementation [2]. Link: [1] https://github.com/OP-TEE/optee_os/commit/a58c4d706d2333d2b21a3eba7e2ec0cb257bca1d Link: [2] https://github.com/ARM-software/SCP-firmware.git Change-Id: I416c7dab5c67954c6fe80bae8d8cdfdcda66873e Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
-
Etienne Carriere authored
Adds SCMI reset domain protocol support in the SCMI message drivers as defined in SCMI specification v2.0 [1]. Not all the messages defined in the specification are supported. scmi_msg_get_rd_handler() sanitizes the message_id value against any speculative use of reset domain ID as a index since by SCMI specification, IDs are indices. This implementation is based on the OP-TEE project implementation [2] itself based on the SCP-firmware implementation [3] of the SCMI protocol server side. Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf Link: [2] https://github.com/OP-TEE/optee_os/commit/56a1f10ed99d683ee3a8af29b6147a59a99ef3e0 Link: [3] https://github.com/ARM-software/SCP-firmware.git Change-Id: If7cf13de40a815dedb40dcd5af8b6bb6725d9078 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
-
Etienne Carriere authored
Adds SCMI clock protocol support in the SCMI message drivers as defined in SCMI specification v2.0 [1] for clock protocol messages. Platform can provide one of the plat_scmi_clock_*() handler for the supported operations set/get state/rate and others. scmi_msg_get_clock_handler() sanitizes the message_id value against any speculative use of clock ID as a index since by SCMI specification, IDs are indices. This implementation is based on the OP-TEE project implementation [2] itself based on the SCP-firmware implementation [3] of the SCMI protocol server side. Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf Link: [2] https://github.com/OP-TEE/optee_os/commit/a7a9e3ba71dd908aafdc4c5ed9b29b15faa9692d Link: [3] https://github.com/ARM-software/SCP-firmware.git Change-Id: Ib56e096512042d4f7b9563d1e4181554eb8ed02c Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
-
Etienne Carriere authored
This change introduces drivers to allow a platform to create a basic SCMI service and register handlers for client request (SCMI agent) on system resources. This is the first piece of the drivers: an entry function, the SCMI base protocol support and helpers for create the response message. With this change, scmi_process_message() is the entry function to process an incoming SCMI message. The function expect the message is already copied from shared memory into secure memory. The message structure stores message reference and output buffer reference where response message shall be stored. scmi_process_message() calls the SCMI protocol driver according to the protocol ID in the message. The SCMI protocol driver will call defined platform handlers according to the message content. This change introduces only the SCMI base protocol as defined in SCMI specification v2.0 [1]. Not all the messages defined in the specification are supported. The SCMI message implementation is derived from the OP-TEE project [2] itself based on the SCP-firmware implementation [3] of the SCMI protocol server side. Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf Link: [2] https://github.com/OP-TEE/optee_os/commit/ae8c8068098d291e6e55744dbc237ec39fd9840a Link: [3] https://github.com/ARM-software/SCP-firmware/tree/v2.6.0 Change-Id: I639c4154a39fca60606264baf8d32452641f45e9 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
-
- 03 Jun, 2020 1 commit
-
-
Etienne Carriere authored
ETZPC stands for Extended TrustZone Protection Controller. It is a resource conditional access device. It is mainly based on Arm TZPC. ST ETZPC exposes memory mapped DECPROT cells to set access permissions to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some of the SoC internal memories. ST ETZPC exposes memory mapped TZMA cells to set access permissions to some SoC internal memories. Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570 Co-developed-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-
- 01 Jun, 2020 1 commit
-
-
Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-
- 11 May, 2020 1 commit
-
-
Etienne Carriere authored
Oscillators, PLLs and some system clocks can be related straight to a parent clock. Prior this change were only oscillators and few clocks supported by this look up. This changes adds PLLs and other system clocks. This enables for flexible use of clock tree exploration when computing a clock frequency value. Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-
- 28 Apr, 2020 1 commit
-
-
Andre Przywara authored
The device tree parsing code for the STM32 platform is using its own FDT helper functions, some of them being rather generic. In particular the existing fdt_read_uint32_array() implementation is now almost identical to the new generic code in fdt_wrappers.c, so we can remove the ST specific version and adjust the existing callers. Compared to the original ST implementation the new version takes a pointer to the DTB as the first argument, and also swaps the order of the number of cells and the pointer. Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
- 25 Feb, 2020 1 commit
-
-
Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
- 20 Jan, 2020 3 commits
-
-
Lionel Debieve authored
Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations. Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
-
Lionel Debieve authored
Add fmc2_nand driver support. The driver implements only read interface for NAND devices. Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
-
Lionel Debieve authored
Device size could be more than 4GB, we must define size as unsigned long long. Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
-
- 03 Oct, 2019 1 commit
-
-
Yann Gautier authored
Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 20 Sep, 2019 2 commits
-
-
Lionel Debieve authored
This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
-
Lionel Debieve authored
The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
-
- 02 Sep, 2019 2 commits
-
-
Yann Gautier authored
If the max-frequency property is provided in the device tree mmc node, it should be managed. The max allowed frequency will be the min between this property value and what the card can support. Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
Yann Gautier authored
Introduce driver for STM32 IWDG peripheral (Independent Watchdog). It is configured according to device tree content and should be enabled from there. The watchdog is not started by default. It can be started after an HW reset if the dedicated OTP is fused. The watchdog also needs to be frozen if a debugger is attached. This is done by configuring the correct bits in DBGMCU. This configuration is allowed by checking BSEC properties. An increase of BL2 size is also required when adding this new code. Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
-
- 01 Aug, 2019 1 commit
-
-
Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 17 Jun, 2019 2 commits
-
-
Yann Gautier authored
Rework the macro that eases the table definition: the src and msk fields are now using MASK and SHIFT defines of each source register. Some macros had then to be modified: _USART1_SEL, _ASS_SEL and _MSS_SEL to _UART1_SEL, _AXIS_SEL, and _MCUS_SEL to match register fields. Note: the mask for RCC_ASSCKSELR_AXISSRC is changed from 0x3 to 0x7 to reflect the size of the register field, even if there are only 3 possible clock sources. The mask value is also corrected for QSPI and FMC clock selection. Change-Id: I44114e3c1dd37b9fa1be1ba519611abd9a07764c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-
Yann Gautier authored
Those functions are generic for parsing nodes from device tree hence could be located in generic source file. The oscillators description structure is also moved to STM32MP1 clock driver, as it is no more used in stm32mp1_clkfunc and cannot be in a generic file. Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 20 Feb, 2019 1 commit
-
-
Yann Gautier authored
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 14 Feb, 2019 6 commits
-
-
Yann Gautier authored
Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks. Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
-
Yann Gautier authored
This change makes the platform to panic in case of peripheral reset resource malfunction. Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
-
Yann Gautier authored
Create a new file stm32mp_clkfunc.c to put functions that could be common between several platforms. Change-Id: Ica915c796b162b2345056b33328acc05035a242c Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
Yann Gautier authored
Regulator configuration at boot takes more information from DT. I2C configuration from DT is done in I2C driver. I2C driver manages more transfer modes. The min voltage of buck1 should also be increased to 1.2V, else the platform does not boot. Heavily modifies stm32_i2c.c since many functions move inside the source file to remove redundant declarations. Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
-
Yann Gautier authored
Remove the previously use function: get_timer, and use new functions timeout_init_us and timeout_elapsed. Change-Id: I4e95b123648bff7ca91e40462a2a3ae24cfe1697 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
-
Yann Gautier authored
Mainly remove suffix 1 from prefix stm32mp1 in several macros and functions that can be used in drivers shared by different platforms. Change-Id: I2295c44f5b1edac7e80a93c0e8dfd671b36e88e7 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-
- 18 Jan, 2019 6 commits
-
-
Yann Gautier authored
The BSEC (Boot and Security and OTP control) is intended to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters. Change-Id: I38c44684c7b9c6a1f24ec0ae3fe99cec481d5a51 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
-
Yann Gautier authored
Change fdt_check_status function to fdt_get_status. Update GPIO defines. Move some functions in gpio driver, instead of dt helper file. Add GPIO bank helper functions. Use only one status field in dt_node_info structure including both status and secure status. Change-Id: I34f93408dd4aac16ae722f564bc3f7d6ae978cf4 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
-
Yann Gautier authored
Reword some traces. Use uintptr_t where required. Reduce scope of variables. Improve io_stm32image algo. Complete some IP registers definitions. Add failure on supported DDR (stm32mp1_ddr_init()). Fix cache flush on cache disable (stm32mp1_ddr_setup). Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
-
Yann Gautier authored
Change-Id: I4a1b281925e0a3a1e2a34b3e363537e4a7f13823 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
-
Yann Gautier authored
The drivers are also updated to reflect the changes. Set RCC as non-secure. Change-Id: I568fa1f418355830ad1d4d1cdcdb910fb362231b Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
Yann Gautier authored
This is the correct name of the IP. Rename stm32mp1_pmic files to stm32mp_pmic. Change-Id: I238a7d1f9a1d099daf7788dc9ebbd3146ba2f15f Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 07 Jan, 2019 1 commit
-
-
Yann Gautier authored
Instead, only platform_def.h is included. The required files to be included are added in stm32mp1_def.h. Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 04 Jan, 2019 1 commit
-
-
Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-