GitLab

Replace the remaining ad-hoc register addresses with proper macros.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: If125f0c8ef77ed280107324edaa05f21979a2c27

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I44d48ad59293562539a0c1d8ffd66333714e041e

Move the DBSC write enabling and disabling to dbsc_setting() function,
to make it local, instead of having it all over the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: If8e5657c3230b5d82b551cb89b11c4d13a2d096b

Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: If54e770ce81c9a6610cd89c3d5f01ea9b96af521

Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
loop can operate over incrementing sequence of addresses just fine.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I5f797024c76f2c18b160ac50ede9e1eac24e6652

Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I2559c5ceb06505361d026ebc1b762bebe17d920b

Use common qos_regs.h instead of a local copy in the D3 QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie22a81bf5cbf3f8970c6e3fbb43ef52c26fb7168

Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I08c033b317685bef7537eb49de160e827b7791ad

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Icd3e12f814d4fdcddaec2d1415f0bbf92169284b

Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6fe03e16c63278aa6fc1bbcc72c07a450d3b7638

The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6d268eae8df5794511d5211e5a59a36291adab3e

Use common qos_regs.h instead of a local copy in the M3N QoS init.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9670c9cdb320d6724175c22210d048af54490b47

Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifd397962c40d174c3af31cb440241cc8bd9335d3

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Idf26cf064e99e95f0140dd747183efe6a6d7f0bf

Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4460c55bf58f33ca72c9bbad99a28b5e4ef7421e

The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I086ab1f457866f0e2c3ccd67609c0be35631f893

Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
loop can operate over incrementing sequence of addresses just fine.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I41728b30087996edc9799f320bf6a3b4465538bd

Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I21c18e80ab9225837e5553dadcf196605e878143

Use common qos_regs.h instead of a local copy in the M3W QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I91175c86cdb94b9271c880df2cb65949f15f1bad

Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I605109b5e41219473a4cbc4a1929b84377ba0b67

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4d8926eb3c44c61ec777c05c581ce8247f13daa6

Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9e3d025567ff4e10e2b4448e8a518b4eee13f6c5

The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7b55a6fa53145ff0427e05656234917f486031df

Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
loop can operate over incrementing sequence of addresses just fine.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I379a1a5dfe2095d9477b364393ab120c4d8e1ba4

Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia92abe11c425220a065d707c350644c955efef92

Use common qos_regs.h instead of a local copy in the H3 QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0b5ceab71be07e270885bdff403e5292e3373787

Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I18556973937d150b60453f9150d54ee612571e35

BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and
BL2.

Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Also sort alphabetically the links at the bottom, a couple of them were
not sorted.

Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

* changes:
  ti: k3: common: Remove coherency workaround for AM65x
  ti: k3: common: Use coherent memory for shared data

Provide the friendly marketing names, not just the platform name.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id4427abb73d0c1be4ac1709b2a8e87beffc20dd5

When acquiring or releasing the power domain locks for a given CPU the
parent nodes are looked up by walking the up the PD tree list on both the
acquire and release path, only one set of lookups is needed. Fetch the
parent nodes first and pass this list into both the acquire and release
functions to avoid the double lookup.

This also allows us to not have to do this lookup after coherency has
been exited during the core power down sequence. The shared struct
psci_cpu_pd_nodes is not placed in coherent memory like is done
for psci_non_cpu_pd_nodes and doing so would negatively affect
performance. With this patch we remove the need to have it in coherent
memory by moving the access out of psci_release_pwr_domain_locks().
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I7b9cfa9d31148dea0f5e21091c8b45ef7fe4c4ab

Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html



Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>