1. 26 Nov, 2018 2 commits
  2. 23 Nov, 2018 2 commits
  3. 22 Nov, 2018 4 commits
  4. 21 Nov, 2018 2 commits
  5. 20 Nov, 2018 5 commits
  6. 19 Nov, 2018 4 commits
  7. 16 Nov, 2018 1 commit
  8. 15 Nov, 2018 10 commits
  9. 14 Nov, 2018 7 commits
    • Andre Przywara's avatar
      allwinner: power: Add DCDC6 power rail · 793c38f0
      Andre Przywara authored
      
      
      The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is
      on by default and uses the default voltage.
      
      As there seems to be at least on board using a different voltage, add
      the rail to the list of known voltage lines, so we can setup the right
      voltage as early as possible.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      793c38f0
    • Andre Przywara's avatar
      allwinner: power: add enable switches for DCDC1/5 · a561e41b
      Andre Przywara authored
      
      
      The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
      isn't critical, since those rails are on by default (and are needed for
      every board), but it is inconsistent.
      
      Add the respective enable bits for those two rails.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      a561e41b
    • Andre Przywara's avatar
      allwinner: power: fix DRIVEVBUS pin setup · d93eb446
      Andre Przywara authored
      
      
      The DRIVEVBUS pin setup was broken in two ways:
      - To configure this pin as an output pin, one has to *clear* the bit in
        register 0x8f. It is 0 by default, but rebooting from Linux might have
        left this bit set.
      - Doing this just configures the pin as an output pin, but doesn't
        actually drive power to it. This is done via bit 2 in register 0x30.
      
      Fix the routine to both properly configure the pin and drive power to
      it. Add an axp_clrsetbits() helper on the way.
      
      Now this isn't really perfect, still:
      We only need to setup the PMIC power rails that are needed for U-Boot.
      DRIVEVBUS typically controls the VBUS voltage for the host function of
      an USB-OTG port, something we typically don't want in U-Boot (fastboot,
      using the USB *device* functionality, is much more common). The
      BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
      actually controls the power of both its USB ports via this line.
      
      Technically we should differentiate here: if DRIVEVBUS controls a
      microUSB-B socket, the power should stay off, any host-type A sockets
      should be supplied, though.
      For now just always enable the power, that shouldn't really hurt the
      USB-OTG functionality anyway.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      d93eb446
    • Andre Przywara's avatar
      allwinner: A64/H5: setup missing bus clocks · 19a7507a
      Andre Przywara authored
      
      
      The legacy Allwinner ATF port used to setup some clocks, and U-Boot is
      still relying on this. We don't need to setup the full set, as the SPL
      is doing most of it, but it misses one clock (AHB2) and programs another
      (AHB1) to quite conservative values.
      
      Fix this up during the platform setup to improve USB and Ethernet
      performance, iperf values go up by 31% in my setup with that patch.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      19a7507a
    • Sughosh Ganu's avatar
      SPM: Raise running priority of the core while in Secure Partition · 6e3bad36
      Sughosh Ganu authored
      
      
      The current secure partition design mandates that a) at a point, only
      a single core can be executing in the secure partition, and b) a core
      cannot be preempted by an interrupt while executing in secure
      partition.
      
      Ensure this by activating the SPM priority prior to entering the
      parition. Deactivate the priority on return from the
      partition.
      
      Change-Id: Icb3473496d16b733564592eef06304a1028e4f5c
      Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      6e3bad36
    • Sughosh Ganu's avatar
      SPM: Register Secure Partition priority level with ehf module · 5681b292
      Sughosh Ganu authored
      
      
      Register a priority level, PLAT_SP_PRI, for secure partition with EL3
      exception handling framework(ehf) module.
      
      The secure partition manager(SPM) would raise the core's priority to
      PLAT_SP_PRI before entering the secure partition, to protect the core
      from getting interrupted while in secure partition.
      
      Change-Id: I686897f052a4371e0efa9b929c07d3ad77249e95
      Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      5681b292
    • Sughosh Ganu's avatar
      SPM: EHF: Build EHF module along with Secure Partition Manager · 8a3588a7
      Sughosh Ganu authored
      
      
      Add a dependency for building EL3 exception handling framework(EHF)
      module with the secure partition manager(SPM).
      
      The EHF module is needed for raising the core's running priority
      before the core enters the secure partition, and lowering it
      subsequently on exit from the secure partition.
      
      Change-Id: Icbe2d0a63f00b46dc593ff3d86b676c9333506c3
      Signed-off-by: default avatarSughosh Ganu <sughosh.ganu@arm.com>
      8a3588a7
  10. 13 Nov, 2018 3 commits