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  1. 13 Aug, 2021 1 commit
    • Pali Rohár's avatar
      refactor(plat/ea_handler): Use default ea handler implementation for panic · 30e8fa7e
      Pali Rohár authored 
      
Put default ea handler implementation into function plat_default_ea_handler()
which just print verbose information and panic, so it can be called also
from overwritten / weak function plat_ea_handler() implementation.

Replace every custom implementation of printing verbose error message of
external aborts in custom plat_ea_handler() functions by a common
implementation from plat_default_ea_handler() function.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
      30e8fa7e
  3. 06 Aug, 2021 1 commit
  5. 05 Aug, 2021 1 commit
  7. 03 Aug, 2021 3 commits
  9. 02 Aug, 2021 5 commits
  11. 23 Jul, 2021 3 commits
  13. 20 Jul, 2021 1 commit
    • Pali Rohár's avatar
      feat(common/debug): add new macro ERROR_NL() to print just a newline · fd1360a3
      Pali Rohár authored 
      
Existing macro ERROR() prints string "ERROR" followed by string
specified by caller. Therefore via this existing macro it is not
possible to end incomplete / existing line by a newline character.

This change adds a new macro ERROR_NL() which prints just a newline
character without any prefix. Implementation of this macro is done via a
new function tf_log_newline() which based on supplied log level either
return or print newline character.

If needed in future based on this tf_log_newline() function can be
defined also macros for other log levels.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I05414ca177f94cdc0f6077394d9c4af4a4382306
      fd1360a3
  15. 16 Jul, 2021 1 commit
  17. 13 Jul, 2021 2 commits
  19. 09 Jul, 2021 1 commit
  21. 29 Jun, 2021 1 commit
  23. 28 Jun, 2021 1 commit
    • Max Shvetsov's avatar
      feat(sve): enable SVE for the secure world · 0c5e7d1c
      Max Shvetsov authored 
      
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
      0c5e7d1c
  25. 23 Jun, 2021 2 commits
  27. 22 Jun, 2021 1 commit
    • Chris Kay's avatar
      refactor(aarch64): remove `FEAT_BTI` architecture check · 4429b471
      Chris Kay authored 
      
BTI instructions are a part of the NOP space in earlier architecture
versions, so it's not inherently incorrect to enable BTI code
or instructions even if the target architecture does not support them.

This change reduces our reliance on architecture versions when checking
for features.

Change-Id: I79f884eec3d65978c61e72e4268021040fd6c96e
Signed-off-by: default avatarChris Kay <chris.kay@arm.com>
      4429b471
  29. 14 Jun, 2021 1 commit
  31. 04 Jun, 2021 2 commits
  33. 02 Jun, 2021 1 commit
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART parent clock rate determination · 5a91c439
      Pali Rohár authored 
      
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
      5a91c439
  35. 28 May, 2021 1 commit
  37. 27 May, 2021 2 commits
  39. 25 May, 2021 1 commit
  41. 19 May, 2021 1 commit
    • Manish V Badarkhe's avatar
      feat(hw_crc): add support for HW computed CRC · a1cedadf
      Manish V Badarkhe authored 
      
Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).

HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.

HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.

HW CRC calculation support will be used in the upcoming
firmware update patches.

Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      a1cedadf
  43. 17 May, 2021 1 commit
  45. 14 May, 2021 1 commit
    • Alexei Fedorov's avatar
      fix(security): Set MDCR_EL3.MCCD bit · 12f6c064
      Alexei Fedorov authored 
      
This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common'
macro to disable cycle counting by PMCCNTR_EL0 in EL3 when
FEAT_PMUv3p7 is implemented. This fixes failing test
'Leak PMU CYCLE counter values from EL3 on PSCI suspend SMC'
on FVP models with 'has_v8_7_pmu_extension' parameter set to
1 or 2.
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I2ad3ef501b31ee11306f76cb5a61032ecfd0fbda
      12f6c064
  47. 13 May, 2021 1 commit
    • Daniel Boulby's avatar
      feat(spmd): add support for FFA_SPM_ID_GET · 70c121a2
      Daniel Boulby authored 
      
Handle calls to the FFA_SPM_ID_GET interface. If FFA_SPM_ID_GET is
invoked from the non-secure physical FF-A instance, return the SPMC id
(defined in the SPMC manifest). If FFA_SPM_ID_GET is invoked from
the secure physical FF-A instance (e.g. the SPMC), return the SPMD id.

Change-Id: Id6d4e96b1da2510386d344e09c4553dba01227ec
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      70c121a2
  49. 29 Apr, 2021 1 commit
  51. 28 Apr, 2021 3 commits
    • David Horstmann's avatar
      refactor(plat/arm): store UUID as a string, rather than ints · 7d111d99
      David Horstmann authored 
      
NOTE: Breaking change to the way UUIDs are stored in the DT

Currently, UUIDs are stored in the device tree as
sequences of 4 integers. There is a mismatch in endianness
between the way UUIDs are represented in memory and the way
they are parsed from the device tree. As a result, we must either
store the UUIDs in little-endian format in the DT (which means
that they do not match up with their string representations)
or perform endianness conversion after parsing them.

Currently, TF-A chooses the second option, with unwieldy
endianness-conversion taking place after reading a UUID.

To fix this problem, and to make it convenient to copy and
paste UUIDs from other tools, change to store UUIDs in string
format, using a new wrapper function to parse them from the
device tree.

Change-Id: I38bd63c907be14e412f03ef0aab9dcabfba0eaa0
Signed-off-by: default avatarDavid Horstmann <david.horstmann@arm.com>
      7d111d99
    • David Horstmann's avatar
      feat(fdt): introduce wrapper function to read DT UUIDs · d13dbb6f
      David Horstmann authored 
      
TF-A does not have the capability to read UUIDs in string form
from the device tree. This capability is useful for readability,
so add a wrapper function, fdtw_read_uuid() to parse UUIDs from
the DT.
This function should parse a string of the form:

"aabbccdd-eeff-4099-8877-665544332211"

to the byte sequence in memory:

[aa bb cc dd ee ff 40 99 88 77 66 55 44 33 22 11]

Change-Id: I99a92fbeb40f4f4713f3458b36cb3863354d2bdf
Signed-off-by: default avatarDavid Horstmann <david.horstmann@arm.com>
      d13dbb6f
    • Manish V Badarkhe's avatar
      refactor(plat/arm): replace FIP base and size macro with a generic name · 49e9ac28
      Manish V Badarkhe authored 
      
Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a
generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE
so that these macros can be reused in the subsequent GPT based support
changes.

Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      49e9ac28