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We must guarantee that writes have become effective before returning to
the caller. Hence, wait for PMUFW signaling completion of the FW call
before returning to the rich OS.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Add support to provide silicon id to non-secure
software through SMC.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

[ sb
Move zynqmp_get_silicon_id outside of compile guards to avoid build
errors.
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide
the Access to the xilfpga library to load the bitstream into zynqmp
PL region.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>

This patch adds a new pm ID to sync with PMUFW ID numbers.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

During system suspend, identify slaves which are configured
as wake sources and call pm_set_wakeup_source API for each of them.

Identifying if device may wake the system is done by checking if any
interrupt of that device is enabled in GICD_ISENABLER when the APU is
about to enter SUSPEND_TO_RAM state. If such interrupt is found,
pm_set_wakeup_source is called with corresponding PM node ID as
argument.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>

The state argument of the pm_self_suspend API encodes the state to
which the APU intends to suspend. The state can be:
- PM_APU_STATE_CPU_IDLE - processor power down, all memories remain
  on
- PM_APU_STATE_SUSPEND_TO_RAM - all processors powered down, L2$
  powered down, all OCM banks in retention and DDR in
  self-refresh.
The calls for setting requirements for L2$ and OCM banks are now
redundant and removed.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
[ sb
 - remove redundant #defines
]
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>

Implementation is based on arm_validate_power_state().
This function is called during CPU_SUSPEND PSCI call to validate
power_state parameter. If state is valid this function populate it
in req_state array as power domain level specific local state.
ATF platform migration guide chapter 2.2 defines this function as
mandatory for PSCIv1.0 CPU_SUSPEND support.
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>

When moving the ATF into the DRAM address space an additional
translation table is required.
Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

The OCM space was reorganized to use the space more efficiently. Adjust
the default ATF location to be aligned with other ZynqMP software
components.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Arm provided error injection support. To enable this error injection,
we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in
CPUACTLR_EL1 register.

This is needed for our cortexa53 edac linux driver testing.
These registers need write access from non secure EL1 i.e linux
at the time of setting the above bits.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>

ZynqMP only supports builds with RESET_TO_BL31=1. Set this option
through the platform makefile on default.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Nodes represent IPI dedicated to the RPU (not accessible by APU)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>

Initialize the generic_delay_timer in the zynqmp port.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

rockchip: fix the scu idle for rk3399

As rk3399 reported the d8/octane scores drop 10% with cpu idle.
The root cause is thc cpu cluster enter the slow mode.
We don't need switch the clock to 24MHz if cpu cluster enter the
retention mode. In order to improve performance, it just needs for
cluster enter powering off mode.

Also, we shouldn't do anything for hlvl if the system is off.

Change-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119

Fixes for AArch32 port of TF

This patch fixes a bug in context management library when writing
SCTLR register during context initialization. The write happened
prior to initialization of the register context pointer. This
resulted in the compiler optimizing the write sequence from the
final binary and hence SCTLR remains uninitialized when
entering normal world. The bug is fixed by doing the
initialization of the register context pointer earlier in the
sequence.

Change-Id: Ic7465593a74534046b79f40446ffa1165c52ed76

This patch resolves a build error in Trusted Firmware when `ARCH=aarch32`
and LOG_LEVEL >= 50.

Change-Id: I62a23ded4a25304533cdcc5ff11442aee041709b

Remove looping around `plat_report_exception`

Automatically select initial xlation lookup level

Move pmf headers to include/lib/pmf and add assembler helper

fiptool: Fix typo in create and update usage functions

Fixes suspend/resume bugs

Given the service name and timestamp id, this assembler macro
calculates the offset into a memory region where the per-cpu timestamp
value is located.

Change-Id: I47f6dfa2a17be182675e2ca0489d6eed42433209

More headers will be needed soon so better to move these to their own
directory to avoid cluttering include/lib.

Change-Id: I6a72dc5b602d6f51954cf60aadd1beb52a268670

rockchip: add dram driver for rk3399

It should be 'fiptool' instead of 'fiptfool'.

Change-Id: I84ce1b6aaae5b8b33e5781bfe4f9e9cf462edb03

For the PMU design, we don't expect to get the interrupts before enter
the power mode. Since that will cause the confusion for the state
machine in the power mode.

Change-Id: Id8dee79ae617a66271b5caf92caf35f520f45099

Change-Id: I986d64df9dc62354d50ccea0468b90f090a44160
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

If we don't enable the Schmitt trigger on the 32 kHz clock then systems
won't always resume from suspend properly.  Presumably anything else in
the system that relies on the 32 kHz clock also will have problems
without the Schmitt trigger enabled.

Enable it always since having the 32 kHz clock on GPIO0_A0 isn't
exactly an optional feature, so all boards using rk3399 will need this.

Change-Id: Idc18c6cd1adc5be5f60efd9cb805d83d5cd40129

add auto_pd_dis_freq parameter, we can pass a frequency from kernel
to disable or enable ddr auto power down function.

Change-Id: Ie30914701336c59047c380381c6b75dd76a89562

add dram driver, and kernel can through sip function talk to bl31 to
do ddr frequency scaling. and ddr auto powerdown.

Change-Id: I0d0f2869aed95e336c6e23ba96a9310985c84840

In a previous change we mistakenly thought that PMU_24M_EN_CFG directly
controlled whether the PMU counts ran off the 32k vs. 24M clock.
Apparently that's not true.  Real logic is now documented in code.

Also in the previous change we mistaknely though that PMU_24M_EN_CFG was
normally supposed to be 1 and we should "restore" it at resume time.
This is a terrible idea and made the system totally unreliable after
resume.  Apparently PMU_24M_EN_CFG should always be 0 with all the
current code and settings.

Let's fix the above two problems.  While we're changing all of this,
let's also:

1. Init at boot time.  Many of these counts are used when the system is
   running normally.  We want the behavior at boot to match the behavior
   after suspend/resume.

2. Init CPU counts to be 1 us.  Although old code was trying to set this
   to 1 ms (1000x slower) at suspend/resume time, we've been testing the
   kernel with 1 us for a long time now.  That's because the kernel (at
   boot time) set these values to 24.  Let's keep at 24 until we know
   that's wrong.

3. Init GPU counts to be 1 us.  Old code wasn't touching the GPU, but as
   documented in comments it makes sense to init here.  Do it.

4. Document the crap out of this code, since the SoC's behavior is
   confusing and poorly documented in the TRM.

5. Increase some stabilization times to 30 ms (from 3 ms).  It's unclear
   that a full 30 ms is needed, but let's be safe for now.

This also inits the counts for the GPU.

(Thanks to Doug's patch that come from https://crosreview.com/372381)

Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22

Instead of hardcoding a level 1 table as the base translation level
table, let the code decide which level is the most appropriate given
the virtual address space size.

As the table granularity is 4 KB, this allows the code to select
level 0, 1 or 2 as base level for AArch64. This way, instead of
limiting the virtual address space width to 39-31 bits, widths of
48-25 bit can be used.

For AArch32, this change allows the code to select level 1 or 2
as the base translation level table and use virtual address space
width of 32-25 bits.

Also removed some unused definitions related to translation tables.

Fixes ARM-software/tf-issues#362

Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65

This patch removes the tight loop that calls `plat_report_exception`
in unhandled exceptions in AArch64 state.
The new behaviour is to call the `plat_report_exception` only
once followed by call to `plat_panic_handler`.
This allows platforms to take platform-specific action when
there is an unhandled exception, instead of always spinning
in a tight loop.

Note: This is a subtle break in behaviour for platforms that
      expect `plat_report_exception` to be continuously executed
      when there is an unhandled exception.

Change-Id: Ie2453804b9b7caf9b010ee73e1a90eeb8384e4e8

Add WFI in platform's unexpected error handlers

This patch adds a WFI instruction in the default implementations of
plat_error_handler() and plat_panic_handler(). This potentially reduces
power consumption by allowing the hardware to enter a low-power state.
The same change has been made to the FVP and Juno platform ports.

Change-Id: Ia4e6e1e5bf1ed42efbba7d0ebbad7be8d5f9f173

Remove dcache invalidation after image authentication