- 20 Oct, 2020 1 commit
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Usama Arif authored
This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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- 24 Sep, 2020 1 commit
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Usama Arif authored
Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 27 May, 2020 1 commit
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Usama Arif authored
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 23 Apr, 2020 1 commit
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Aditya Angadi authored
RD-Daniel Config-XLR platform has four identical chips connected via a high speed coherent CCIX link. Each chip has four Neoverse cores connected via coherent CMN interconnect. Change-Id: I37d1b91f2b6ba08f61c64d0288bc16a429836c08 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 26 Mar, 2020 1 commit
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Oliver Swede authored
This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
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