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The SPM implementation based on MM is going to be kept for the
foreseeable future.

Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>

Enable the deprecated SPM framework for the SynQuacer platform.
It involves creating a memory layout in secure DRAM, and wiring
up the SPM infrastructure so that the secure partition payload
that is loaded into this region by the SCP firmware is dispatched
appropriately.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

The logic that initializes the BL32 entry point data structure
should only be executed if we are in fact loading OP-TEE, and
not if BL32_BASE is set for other reasons (i.e., when enabling
SPM)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

- Remove references to removed build options.
- Update Makefile paths.
- Migrate to bl31_early_platform_setup2().

Change-Id: I51cbf09a0297ac1ee645a959063238c9d556d8e1
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>

Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>