- 06 Jul, 2021 1 commit
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Garmin Chang authored
DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. 1. Add MCUSYS related DCM drivers. 2. Enable MCUSYS related DCM by default. Change-Id: I3237199bc217bd3682f51d31284db5fd0324b396 Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
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- 02 Jul, 2021 4 commits
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Edward-JW Yang authored
Support DRAM/MAINPLL/26M off when system suspend. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77
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Edward-JW Yang authored
Add drivers to support MCUSYS off when system suspend. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
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Elly Chiang authored
Add PTP3 drivers to protect CPU excessive voltage drop in CPU heavy loading. Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d Signed-off-by: Elly Chiang <elly.chiang@mediatek.com>
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Tinghan Shen authored
In mt8195 suspend/resume flow, ATF has to communicate with a subsys by read/write the subsys registers. However, the register region of subsys doesn't include in the MMU mapping region. It triggers MMU faults. This patch extends the MMU region 0 size to cover all mt8195 HW modules. This patch also remove MMU region 1 because region 0 covers region 1. Change-Id: I3a186ed71d0d963b59ae55e27a6d27a01fe4f638 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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- 26 May, 2021 1 commit
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Rex-BC Chen authored
MTK display port mute/unmute control registers need to be set in secure world. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
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- 23 Apr, 2021 13 commits
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Yidi Lin authored
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the driver with mt8195. Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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Yidi Lin authored
mt8195 also uses PMIC mt6359p. The only difference is the pwrap register definition. Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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Yidi Lin authored
Add system_reset function in PSCI ops Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I177796e30198b0a53402093ee0917dda43074385
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mtk20895 authored
Add gpio driver. Signed-off-by: mtk20895 <zhiqiang.ma@mediatek.com> Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
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Yidi Lin authored
Add the basic SiP service Change-Id: I21fe9d85eac4be9101b12c4b6c28294c5b93cb5f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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James Liao authored
Implement PSCI platform OPs to support CPU hotplug and MCDI. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Change-Id: I1321f7989c8a3d116d698768a7146e8f180ee9c0
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James Liao authored
Add MCDI related drivers to handle CPU powered on/off in CPU suspend. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Change-Id: I6a6f9bf5d1d8bda1ee603d8bf3fc206437de7ad8
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James Liao authored
Add SPMC driver for CPU power on/off. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Change-Id: If47d7f3f3b9965f3c0402ea6cdb917ad1d16bb32
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Yidi Lin authored
Initialize delay_timer for delay functions. Change-Id: Ib554135151f8b5c642b5a6511c942bb9efc0a47f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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Yidi Lin authored
Change-Id: I7e0fbd04b0cdf5da92b8ef39737342f2d66f5f10 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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gtk_pangao authored
MT8192 cirq driver can be shared with MT8195. Move cirq driver to common common folder. Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com> Change-Id: Iba5cdcfd2116f0bd07e0497250f2da45613e3a4f
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christine.zhu authored
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common and do the initialization. Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.google.com> Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
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Yidi Lin authored
- Add basic platform setup - Add MT8195 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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