- 23 Jan, 2019 15 commits
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Varun Wadekar authored
This patch removes this unused config option from the Tegra186 platform makefiles. Change-Id: Idcdf6854332a26599323a247289c2d3ce19f475f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes the usage of this platform config, as it is always enabled by all the supported platforms. Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch includes the console driver from individual platform makefiles and removes it from tegra_common.mk. This allows future platforms to include consoles of their choice. Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Steven Kao authored
The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform custom steps during TZDRAM setup. Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra186 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Steven Kao authored
This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_* - SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_* NOTE: Future SoCs will have to define these macros to keep the drivers functioning. Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987 Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform platform specific steps, e.g. enable encryption, save base/size to secure scratch registers. Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch fixes the following MISRA violations: Rule 8.6: Externally-linked object or function has "no" definition(s). Rule 11.1: A cast shall not convert a pointer to a function to any other type. Change-Id: Ic1f6fc14c744e54ff782c6987dab9c9430410f5e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch sanity checks the target cluster value, during core power on, by comparing it against the maximum number of clusters supported by the platform. Reported by: Rohit Khanna <rokhanna@nvidia.com> Change-Id: Ia73ccf04bd246403de4ffff6e5c99e3b00fb98ca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
MISRA Rule 8.4, A compatible declaration shall be visible when an object or function with external linkage is defined. This patch adds static for local array to fix this defect. Change-Id: I8231448bf1bc0b1e59611d7645ca983b83d5c8e3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch corrects the logic to read the uncore command/response bits from the command/response values. The previous logic tapped into incorrect bits leading to garbage counter values. Change-Id: Ib8327ca3cb3d2086bb268e9a5366865cdf35b493 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch modifies the timeout loop to use udelay() instead of mdelay(). This helps with the boot time on some platforms which issue a lot of MCE calls and every mdelay adds up increasing the boot time by a lot. Change-Id: Ic50081b73e1cbc2714361235b5c396e294b8f752 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
MISRA Rule 8.3, All declarations of an object or function shall use the same names and type qualifiers. This patch removes unused function(s). Change-Id: I90865c003d46f1dc08bfb5f4fe8a327ea42a2bb7 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Puneet Saxena authored
Introduce platform handlers to program the MSS settings. This allows the current driver to scale to future chips. Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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- 18 Jan, 2019 8 commits
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Anthony Zhou authored
MISRA Rule 10.3, the value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The essential type of a enum member is anonymous enum, the enum member should be casted to the right type when using it. Both UL and ULL suffix equal to uint64_t constant in compiler aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix in platform code. So in some case, cast a constant to uint32_t is necessary. Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Steven Kao authored
This patch adds a hook to get the number of smmu devices and removes the NUM_SMMU_DEVICES macro. Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc41 Signed-off-by: Steven Kao <skao@nvidia.com>
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Steven Kao authored
This patch changes direct writes to ACTLR_ELx registers to use read-modify-write instead. Change-Id: I6e0eaa6974583f3035cb3724088f3f1c849da229 Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
This patch enables the following erratas for Cortex-A57 CPUs: - ERRATA_A57_806969 - ERRATA_A57_813419 - ERRATA_A57_813420 - ERRATA_A57_826974 - ERRATA_A57_826977 - ERRATA_A57_828024 - ERRATA_A57_829520 - ERRATA_A57_833471 Change-Id: Ib18b7654607b967b70082f683686a16f52637442 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Remove unused type conversion Fix invalid use of function pointer [Rule 1.3] Fix variable essential type doesn't match [Rule 10.3] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I23994c9d4d6a240080933d848d2b03865acaa833 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch reduces the code complexity for the platform's 'get_target_pwr_state' handler, by reducing the number of 'if' conditions and adding helper functions to calculate power state for the cluster/system. Tested with 'pmccabe' Change-Id: I32fa4c814bd97f620f2003fa39f1bfceae563771 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds the driver for the general purpose DMA hardware block on newer Tegra SoCs. The GPCDMA is a special purpose DMA used to speed up memory copy operations to/from DRAM and TZSRAM. This patch introduces a macro 'USE_GPC_DMA' to allow platforms to override CPU based memory operations. Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: Ibdae1d18d299562ca2b96b2318b914601c9926b1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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- 16 Jan, 2019 10 commits
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Anthony Zhou authored
This patch removes unused type conversions as all the relevant macros now use U()/ULL(), making these explicit typecasts unnecessary. Change-Id: I01fb534649db2aaf186406b1aef6897662b44fe3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch removes unwanted error prints from the MCE command handler, to reduce the code complexity for this function. Tested with 'pmccabe' Change-Id: I375d289db1df9e119eeb1830210974457c8905a4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes support for the SC8 power state as the feature is no longer required for Tegra186 projects. Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
This patch fixes MISRA defects for the MCE driver. * Using logical NOT for bool type function * Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace MPIDR_CLUSTER_MASK Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The platform code generates the power domain tree. The handler to retrieve the tree should also reside in the platform code. This patch moves the plat_get_power_domain_tree_desc() to the individual platforms. Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 1 commit
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Varun Wadekar authored
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 27 Apr, 2018 1 commit
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Masahiro Yamada authored
Since commit 031dbb12 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 08 Mar, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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