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The upcoming refactoring to support the new H616 SoCs will push the A64
build over the edge, by using more than the 48KB of SRAM available.

To reduce the code size, set some libfdt options that aim to reduce
sanity checks (for saving code space):
- ASSUME_LATEST: only allow v17 DTBs (as created by dtc)
- ASSUME_NO_ROLLBACK: don't prepare for failed DT additions
- ASSUME_LIBFDT_ORDER: assume sane ordering, as done by dtc

Change-Id: I12c93ec09e7587c5ae71e54947f817c32ce5fd6d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

This gives the rich OS the flexibility to choose between I2C and RSB
communication. Since a runtime address can only be assigned once after
entering RSB mode, it also lets the rich OS choose any runtime address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id49c124c5e925985fc31c0ba38c7fb6c941aafa8

None of the other drivers (Linux, U-Boot, Crust) need to lower the bus
clock frequency to switch the PMIC to RSB mode. That logic is not needed
here, either. The hardware takes care of running this transaction at the
correct bus frequency.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idcfe933df4da75d5fd5a4f3e362da40ac26bdad1

The H6 has a "secure port controller" similar to the A64/H5, but with
more ports and a different register layout. Split the platform-specific
parts out into a header, and add the missing MMIO base address.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I3703868bc595459ecf9568b9d1605cb1be014bf5

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.

Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86

The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf

Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.

This changes the signatures of the low-level register read/write
functions to match the interface expected by the common driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I14d63d171a094fa1375904928270fa3e21761646

Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.

Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.

I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.

The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2

This simplifies the code a bit. Verified to produce the same binary.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287

As of a561e41b

 ("allwinner: power: add enable switches for DCDC1/5")
there are no longer regulators without an enable register provided.
Since it seems reasonable that this will continue to be the case, drop
the check.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39

should_enable_regulator() is already checked in the regulators subnode
loop before setup_regulator() is called, so there's no need to check it
again here.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977

These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed before BL31, or it wouldn't be possible to boot.
Allwinner platforms don't generally build anything but BL31 anyway, but
this change improves clarity and consistency with allwinner-common.mk.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf

The function is only used in this file, and it doesn't make sense for it
to be used anywhere else.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f

The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matches the code in sunxi_system_reset().

The two error messages say essentially the same thing anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a

- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in error messages.
- Consistently omit the trailing period.
- No need to print the unknown SoC's ID, since we already did that
  earlier in bl31_platform_setup().
- On the other hand, do print the ID of the unknown PMIC.
- Try to keep the messages concise, as the large string size in these
  files was causing the firmware to spill into the next page.
- Downgrade the banner from NOTICE to INFO. It's purely informational,
  and people should be using debug builds on untested hardware anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb

Ensure that the default (zero) value represents the case where we take
no action. Previously, if a PLAT=sun50i_a64 build was booted on an
unknown SoC ID, it would be treated as an H5 at shutdown.

This removes some duplicate code and fixes error propagation on H6.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc

A64-OLinuXino family boards (maybe others too) uses PG for USB vbus
enable/disable. However PG is supplied by DLDO4, which is not present
in the list of known regulators. This patch adds DLD04 to it.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Change-Id: I31d3bb3e0004ccf5b282d08b530ee44979da0466

So far the DT node describing the AXP803 PMIC used in many Allwinner A64
boards had only one subnode, so our code just entering the first subnode
to find all regulators worked fine.

However recent DT updates in the Linux kernel add more subnodes *before*
that, so we need to make sure to explicitly enter the "regulators"
subnode to find the information we are after.

Improve some DT node parsing error handling on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

This maximizes the amount of data protected by the MMU.
Signed-off-by: Samuel Holland <samuel@sholland.org>

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is
on by default and uses the default voltage.

As there seems to be at least on board using a different voltage, add
the rail to the list of known voltage lines, so we can setup the right
voltage as early as possible.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every board), but it is inconsistent.

Add the respective enable bits for those two rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
  register 0x8f. It is 0 by default, but rebooting from Linux might have
  left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
  actually drive power to it. This is done via bit 2 in register 0x30.

Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.

Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.

Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To avoid this situation, delay the activation of the DC1SW line until
the very end, so those other lines are always activated earlier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.

To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compatible string to find the PMIC node.
- We switch the N_VBUSEN pin if the DT property tells us so.
- We scan over all regulator subnodes, and switch DC1SW if there is at
least one other node referencing it (judging by the existence of a
phandle property in that subnode).
This is just the first part of the setup, a follow up patch will setup
voltages.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use the
information contained therein to setup some initial power rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC,
which allows to programmatically power down the board.

Use the newly introduced RSB driver to detect and program the PMIC on
boot, then later to turn off the main voltage rails when receiving a
PSCI SYSTEM_POWER_OFF command.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Allwinner produces reference board designs, which apparently most board
vendors copy from. So every H5 board I checked uses regulators which are
controlled by the same PortL GPIO pins to power the ARM CPU cores, the
DRAM and the I/O ports.
Add a SoC specific power down routine, which turns those regulators off
when ATF detects running on an H5 SoC and the rich OS triggers a
SYSTEM_POWEROFF PSCI call.

NOTE: It sounds very tempting to turn the CPU power off, but this is not
working as expected, instead the system is rebooting. Most probably this
is due to VCC-SYS also being controlled by the same GPIO line, and
turning this off requires an elaborate and not fully understood setup.
Apparently not even Allwinner reference code is turning this regulator
off. So for now we refrain to pulling down PL8, the power consumption is
quite low anyway, so we are as close to poweroff as reasonably possible.
Many thanks to Samuel for doing some research on that topic.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

So far we have a sunxi_private.h header file in the common code directory.
This holds the prototypes of various functions we share in *common*
code. However we will need some of those in the platform specific code
parts as well, and want to introduce new functions shared across the
whole platform port.

So move the sunxi_private.h file into the common/include directory, so
that it becomes visible to all parts of the platform code.
Fix up the existing #includes and add missing ones, also add the
sunxi_read_soc_id() prototype here.

This will be used in follow up patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Some boards don't have a PMIC, so they can't easily turn their power
off. To cover those boards anyway, let's turn off as many devices and
clocks as possible, so that the power consumption is reduced. Then
halt the last core, as before.
This will later be extended with proper PMIC support for supported
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

In the BL31 platform setup we read the Allwinner SoC ID to identify the
chip and print its name.
In addition to that we will need to differentiate the power setup
between the SoCs, to pass on the SoC ID to the PMIC setup routine.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

For the two different platforms we support in the Allwinner port we
mostly rely on header files covering the differences. This leads to the
platform.mk files in the respective directories to be almost identical.

To avoid further divergence and make sure that one platform doesn't
break accidentally, let's create a shared allwinner-common.mk file and
include that from the platform directory.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Change-Id: I206478597dd9855d3fe1577e7e2c0fe6d2af1cc5
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original placeholder power off code is moved to A64 code, as it's
still TODO to implement PMIC operations for A64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prevent undefined reference.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

The relative VER_REG *offset* is the same across all known SoCs, so we
can define this offset near it's user.

Remove it from the memory map.
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>