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If a PMIC regulator has its DT node disabled, leave the regulator off.

Change-Id: I895f740328e8f11d485829c3a89a9b9f8e5644be
Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>

* changes:
  plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
  plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33

* changes:
  qemu/qemu_sbsa: fix memory type of secure NOR flash
  qemu/qemu_sbsa: spm_mm supports 512 cores

Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e

The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e

when updata routing of an SDEI event, if the registration flags
is SDEI_REGF_RM_PE, need to updata the affinity of shared event.
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Change-Id: Ie5d7cc4199253f6af1c28b407f712caac3092d06

* changes:
  drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
  drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
  drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
  drivers/gicv3: fix logical issue for num_eints
  drivers/gicv3: fix potential GICD context override with ESPI enabled
  drivers/gicv3: use mpidr to probe GICR for current CPU

Make the aarch64's el3_panic() function print a newline character after
PC address, otherwise the output can get mangled in one line with output
from other firmware. Here is an example of how the output of el3_panic()
got mangled with Linux' console output:

    ERROR:   Unhandled External Abort received on 0x80000001 at EL3!
    ERROR:    exception reason=1 syndrome=0x92000210
    PANIC at PC : 0x0000000004027400[13438.473133] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
    [13438.479255] rcu:     1-...0: (4 ticks this GP) idle=35e/1/0x4000000000000000 softirq=146459/146459 fqs=2625

The aarch32 version of this function already does this.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9f0d032c6cd1e2be7a1837f9c8e8244d30633993

* changes:
  mediatek: mt8192: Add Vcore DVFS driver
  mediatek: mt8192: Add SPM suspend driver
  mediatek: mt8192: supports mcusys off when system suspend
  mediatek: mt8192: Add lpm driver

1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a

Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

Supports dram/mainpll/26m off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2

Low Power Management (LPM) helps find a suitable configuration
for letting system entering idle or suspend with the most
resources off.

Change-Id: Ie6a7063b666cf338cff5bc972c9025b26de482eb
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe

Signed-off-by: sah01 <sahil@arm.com>
Change-Id: Ic11d739c0bf2076354716cc06fbe25e9000a21e7

Add basic support for Makalu CPU.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d

* changes:
  plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
  plat/arm: juno: Condition Juno entropy source with CRC instructions

Added GIC600AE FVP model version information.

Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602

sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also increased.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c

ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0.  This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217

* changes:
  plat/marvell/armada: cleanup MSS SRAM if used for copy
  plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
  plat/marvell/armada/common/mss: use MSS SRAM in secure mode
  include/drivers/marvell/mochi: add detection of secure mode
  plat/marvell: fix SPD handling in dram port
  marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
  drivers/marvell/mochi: add support for cn913x in PCIe EP mode
  drivers/marvell/mochi: add missing stream IDs configurations
  plat/marvell/armada/a8k: support HW RNG by SMC
  drivers/rambus: add TRNG-IP-76 driver

This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).

Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099

Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>

The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA.
In secure boot mode the MSS DMA is unable to directly load
the MSS FW image from DRAM to IRAM.
This patch adds support for using the MSS SRAM as intermediate
storage. The MSS FW image is loaded by application CPU into the
MSS SRAM first, then transferred to MSS IRAM by MSS DMA.
Such change allows the CP MSS image load in secure mode.

Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>

MISRA complained about "0"s not being followed by an "U" (please note
my protest about this!) and about values not being explicitly compared
to 0 (fair enough).
Also use explicit pointer types.

Fix those issues to make the CI happy.

Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>