- 15 Jun, 2021 2 commits
-
-
Jiafei Pan authored
Use common code in common file to configure platform. Signed-off-by:Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I72fe22751f12b8a4996a7b9f75fae4c912ea86de
-
Jiafei Pan authored
Move some common make variables to new plat_common_def.mk, then it can be reused by other platforms. Signed-off-by:
-
- 24 Mar, 2021 18 commits
-
-
Pankaj Gupta authored
New NXP platform lx2160a-qds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by:
Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by:
Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
-
Pankaj Gupta authored
New NXP platform lx2160a-rdb(Reference Design Board): - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by:
-
Pankaj Gupta authored
New NXP platform lx2162aqds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by:
-
Pankaj Gupta authored
SoC erratas are handled as part of this commit. Signed-off-by: -
Pankaj Gupta authored
- NXP SoC lx2160a needs additional ddr_fip.bin. - There are three types of ddr image that can be created: -- ddr_fip.mk for creating fip_ddr.bin image for normal boot. -- ddr_fip_sb.mk for creating fip_ddr_sec.bin image for NXP CSF based CoT/secure boot. -- ddr_fip_tbbr.mk for creating fip_ddr_sec.bin image for MBEDTLS CoT/secure boot. Signed-off-by: -
Pankaj Gupta authored
* NXP SoC is 16 A-72 core SoC. * SoC specific defines are defined in: - soc.def - soc.h * Called for BL2 and BL31 setup, SoC specific setup are implemented in: - soc.c * platform specific helper functions implemented at: - aarch64/lx2160a_helpers.S * platform specific functions used by 'plat/nxp/commpon/psci', etc. are implemented at: - aarch64/lx2160a.S * platform specific implementation for handling PSCI_SYSTEM_RESET2: - aarch64/lx2160a_warm_rst.S Signed-off-by:
rocket <rod.dorris@nxp.com> Signed-off-by:
-
Pankaj Gupta authored
- Default header files for: -- plat/nxp/soc-lxxxx/include/soc.h uses: --- soc_default_base_addr.h --- soc_default_base_macros.h -- plat/nxp/soc-lxxxx/<$PLAT>/platform_def.h uses: --- plat_default_def.h: Every macro define can be overidden. -- include/common/tbbr/tbbr_img_def.h uses: --- plat_tbbr_img_def.h: platform specific new FIP image macros. Signed-off-by: -
Pankaj Gupta authored
For NXP platforms: - Setup files for BL2 and BL31 - Other supporting files. Signed-off-by: -
Pankaj Gupta authored
NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2 raised from kernel (> 5.4). As part of first cold boot, DDR training data is stored in NV storage. As part of this SMC handling, following things are done: - DDR is put in self-refresh mode to retain the content of DDR. - Reset cause is saved. - Reset is triggered. On next boot to last warm-reset, DDR training is restored from the NV storage. Signed-off-by:
Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by:
Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by:
-
Pankaj Gupta authored
NV storage API(s) for NXP platforms, supported on: - flexspi-nor - SecMon - General Purpose Registers at Low-Power section, retains their content if backed by coined battery. Signed-off-by: -
Pankaj Gupta authored
NXP SoC supports two TBB mode: - MBED_TLS based -- ROTK key hash is placed as part of the BL2 binary at section: --- .rodata.nxp_rotpk_hash -- Supporting non-volatile counter via SFP. -- platform function used by TFA common authentication code. - NXP CSF based -- ROTK key deployment vary from MBEDTLS Signed-off-by:Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by:
-
Pankaj Gupta authored
All of the NXP SoC, needs fip_fuse image to be loaded additionally as part of preparation for Trusted board boot - fip_fuse.bin contains an image for auto fuse provisioning. - Auto fuse provisioning is based on the input file with values for: -- SRK Hash -- OTPMK -- misc. refer board manual for more details. Signed-off-by: -
Pankaj Gupta authored
Few of the NXP SoC like LX2160A, needs ddr-phy images to be loaded additionally before DDR initialization - fip_ddr.bin is created containing upto 6 ddr images. - With TRUSTED_BOARD_BOOT = 1, fip_ddr.bin is authenticated first before loading and starting DDR initialization. - To successfully compile this image, platform-defined header files needs to be defined: -- include/common/tbbr/tbbr_img_def.h uses: --- plat_tbbr_img_def.h: platform specific new FIP image macros. -- include/tools/share/firmware_image_package.h uses: --- plat_def_fip_uuid.h: platform specific new UUID macros. ---- Added UUID for DDR images to create FIP-DDR. ---- Added UUID for FUSE provisioning images to create FIP-fuse. -- include/tools/share/tbbr_oid.h uses: --- platform_oid.h: platform specific new OID macros. Signed-off-by: -
Pankaj Gupta authored
function load_img(), is dependent on: - Recursively calling load_image() defined in common/bl_common.c - for each image in the fip. Signed-off-by: -
Pankaj Gupta authored
SMC call handling at EL3 due SIP and SVC calls. Signed-off-by:
-
Pankaj Gupta authored
Signed-off-by:
-
Pankaj Gupta authored
Signed-off-by:
-
Pankaj Gupta authored
bl31-data file written in assembly helps to manage data at bl31. Signed-off-by:
-
- 12 Feb, 2021 1 commit
-
-
Pankaj Gupta authored
NXP specifc macro SET_NXP_MAKE_FLAG is added. NXP has pool of multiple IPs. This macro helps: - In soc.mk, this macro help the selected IP source files to be included for that SoC. -- The set of IPs required for one NXP SoC is different to the set of IPs required by another NXP SoC. - For the same SoC, -- For one feature, the IP may be required in both BL2 and BL31. -- Without the above feature, that IP may be required in one. This macro help in selecting the inclusion of source and header files to: --- BL2 only --- BL31 only --- COMM (used by BL2 and BL31) Signed-off-by:
-
