- 27 May, 2016 2 commits
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Caesar Wang authored
There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs on rk3399 platform. The pull direction(pullup or pulldown) for all of GPIOs are software-programmable. At the moment, we add the gpio basic driver since reset or power off the devices from gpio configuration for BL31.
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Caesar Wang authored
On some platform gpio can set/get pull status when input, add these function so we can set/get gpio pull status when need it. And they are optional function.
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- 24 May, 2016 1 commit
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danh-arm authored
Implement generic delay timer and use it on platforms
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- 20 May, 2016 6 commits
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Antonio Nino Diaz authored
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
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Antonio Nino Diaz authored
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e
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Antonio Nino Diaz authored
Added a build flag to select the generic delay timer on FVP instead of the SP804 timer. By default, the generic one will be selected. The user guide has been updated. Change-Id: Ica34425c6d4ed95a187b529c612f6d3b26b78bc6
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Antonio Nino Diaz authored
Add delay timer implementation based on the system generic counter. This either uses the platform's implementation of `plat_get_syscnt_freq()` or explicit clock multiplier/divider values provided by the platform. The current implementation of udelay has been modified to avoid unnecessary calculations while waiting on the loop and to make it easier to check for overflows. Change-Id: I9062e1d506dc2f68367fd9289250b93444721732
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Antonio Nino Diaz authored
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all upstream platforms. Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
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Antonio Nino Diaz authored
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit plat_get_syscnt_freq. The old one has been flagged as deprecated. Common code has been updated to use this new version. Porting guide has been updated. Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e
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- 12 May, 2016 3 commits
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danh-arm authored
Hw crypt v3
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Yi Zheng authored
Change-Id: Idc40cc6243e532567ec4334ae37d97c003c90bfa Signed-off-by: Yi Zheng <yi.zheng@mediatek.com>
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Jimmy Huang authored
Due to the changes in Mediatek platform common code, we need to move plat related SiP functions to plat folder. Change-Id: I6b14b988235205a5858b4bf49043bc79d0512b06 Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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- 11 May, 2016 1 commit
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danh-arm authored
Rockchip: Add some debug assertions in the PMU driver
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- 05 May, 2016 1 commit
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Sandrine Bailleux authored
This patch adds some debug assertions ensuring that array indices are within the bounds of the array. Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a
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- 04 May, 2016 5 commits
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danh-arm authored
rockchip: support the suspend/resume for rk3399
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danh-arm authored
Refactor MediaTek platform common code
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Caesar Wang authored
This patch adds to support the suspend/resume for rk3399 SoCs. Signed-off-by: Shengfei xu <xsf@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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danh-arm authored
FVP: Remove VE memory map support and change default GIC driver
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Leon Chen authored
Refactor MediaTek platform common code for further mt6795 upstream.
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- 28 Apr, 2016 1 commit
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Soby Mathew authored
This patch changes the default driver for FVP platform from the deprecated GICv3 legacy to the GICv3 only driver. This means that the default build of Trusted Firmware will not be able boot Linux kernel with GICv2 FDT blob. The user guide is also updated to reflect this change of default GIC driver for FVP. Change-Id: Id6fc8c1ac16ad633dabb3cd189b690415a047764
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- 27 Apr, 2016 10 commits
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Soby Mathew authored
This patch removes support for legacy Versatile Express memory map for the GIC peripheral in the FVP platform. The user guide is also updated for the same. Change-Id: Ib8cfb819083aca359e5b46b5757cb56cb0ea6533
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danh-arm authored
Emmc v3
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Haojian Zhuang authored
In a lot of embedded platforms, eMMC device is the only one storage device. So loading content from eMMC device is required in ATF. Create the emmc stack that could co-work with IO block driver. Support to read/write/erase eMMC blocks on both rpmb and normal user area. Support to change the IO speed and bus width. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Add MAX_IO_BLOCK_DEVICES in porting guide. It's necessary to define this macro to support io block device. With this macro, multiple block devices could be opened at the same time. Each block device stores its own state. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
FIP is accessed as memory-mapped type. eMMC is block device type. In order to support FIP based on eMMC, add the new io_block layer. io_block always access eMMC device as block size. And it'll only copy the required data into buffer in io_block driver. So preparing an temporary buffer is required. When use io_block device, MAX_IO_BLOCK_DEVICES should be declared in platform_def.h. It's used to support multiple block devices. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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danh-arm authored
Doc: Fix the path to the xlat lib
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danh-arm authored
fip_create: Fix exit status for missing output filename (2)
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danh-arm authored
Fix computation of L1 bitmask in the translation table lib
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Sandrine Bailleux authored
The translation table library code has moved from lib/aarch64/ to lib/xlat_tables/ since commit 3ca9928d but the Porting Guide still points to the old location. This patch fixes this issue. Change-Id: I983a9a100d70eacf6bac71725ffbb4bb5f3732b0
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Brendan Jackman authored
Change-Id: I0d298eea9eaf47121c87637c7395e5d9868aa272
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- 26 Apr, 2016 3 commits
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Sandrine Bailleux authored
This patch fixes the computation of the bitmask used to isolate the level 1 field of a virtual address. The whole computation needs to work on 64-bit values to produce the correct bitmask value. XLAT_TABLE_ENTRIES_MASK being a C constant, it is a 32-bit value so it needs to be extended to a 64-bit value before it takes part in any other computation. This patch fixes this bug by casting XLAT_TABLE_ENTRIES_MASK as an unsigned long long. Note that this bug doesn't manifest itself in practice because address spaces larger than 39 bits are not yet supported in the Trusted Firmware. Change-Id: I955fd263ecb691ca94b29b9c9f576008ce1d87ee
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danh-arm authored
Conditionally compile `plat_get_syscnt_freq()` in ARM standard platforms
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Yatharth Kochar authored
This patch puts the definition of `plat_get_syscnt_freq()` under `#ifdef ARM_SYS_CNTCTL_BASE` in arm_common.c file. This is the fix for compilation error introduced by commit-id `749ade45`, for platforms that use arm_common.c but do not provide a memory mapped interface to the generic counter. Fixes ARM-software/tf-issues#395 Change-Id: I2f2b10bd9500fa15308541ccb15829306a76a745
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- 25 Apr, 2016 6 commits
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danh-arm authored
Validate psci_cpu_on_start() arguments
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danh-arm authored
rockchip: fixes for the required
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danh-arm authored
Move `plat_get_syscnt_freq()` to arm_common.c
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Sandrine Bailleux authored
The "end power level" value passed as the 3rd argument to the psci_cpu_on_start() function is not used so this patch removes it. Change-Id: Icaa68b8c4ecd94507287970455fbff354faaa41e
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Sandrine Bailleux authored
This patch introduces some debug assertions in the function psci_cpu_on_start() to check the arguments it receives are valid. Change-Id: If4d23c9f668fb46f2d18c5e2ed1929498cc6736b
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Caesar Wang authored
This patch has the following change for rk3399. * Set the uart to 115200 since the loader decide to set uart baud to 115200Hz. So the ATF also should set uart baud to 115200. * We need ensure the bl31 base is greater than 4KB since there are have the shared mem for coreboot.(Note: the previous vesion was tested with uboot) Otherwise, we will happen the exception crash since the ddr area won't to work from the shared ram address in some cases. For example, the exception crash: CBFS: Found @ offset 19c80 size 24074 exception _sync_sp_el0 ELR = 0x0000000000008000 ESR = 0x0000000002000000 SPSR = 0x600003cc FAR = 0xffffffff00000000 SP = 0x00000000ff8ed230 ... X29 = 0x00000000ff8c1fc0 X30 = 0x000000000030e3b0 exception death Change-Id: I8bc557c6bcaf6804d2a313b38667d3e2517881d7 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 22 Apr, 2016 1 commit
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danh-arm authored
Cortex-A57 errata workarounds
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