1. 18 Feb, 2020 1 commit
  2. 12 Feb, 2020 1 commit
  3. 07 Feb, 2020 2 commits
    • Vijayenthiran Subramaniam's avatar
      plat/arm/sgi: introduce number of chips macro · 4d37aa76
      Vijayenthiran Subramaniam authored
      
      
      Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
      multi-chip support to define number of chiplets on the platform. By
      default, this flag is set to 1 and does not affect the existing single
      chip platforms.
      
      For multi-chip platforms, override the default value of
      CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
      platform. As an example, the command below sets the number of chiplets
      to two on the RD-N1-Edge multi-chip platform:
      
      export CROSS_COMPILE=<path-to-cross-compiler>
      make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
      
      Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
      Signed-off-by: default avatarVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
      4d37aa76
    • Vijayenthiran Subramaniam's avatar
      board/rdn1edge: add support for dual-chip configuration · 2d4b719c
      Vijayenthiran Subramaniam authored
      
      
      RD-N1-Edge based platforms can operate in dual-chip configuration
      wherein two rdn1edge SoCs are connected through a high speed coherent
      CCIX link.
      
      This patch adds a function to check if the RD-N1-Edge platform is
      operating in multi-chip mode by reading the SID register's NODE_ID
      value. If operating in multi-chip mode, initialize GIC-600 multi-chip
      operation by overriding the default GICR frames with array of GICR
      frames and setting the chip 0 as routing table owner.
      
      The address space of the second RD-N1-Edge chip (chip 1) starts from the
      address 4TB. So increase the physical and virtual address space size to
      43 bits to accommodate the multi-chip configuration. If the multi-chip
      mode configuration is detected, dynamically add mmap entry for the
      peripherals memory region of the second RD-N1-Edge SoC. This is required
      to let the BL31 platform setup stage to configure the devices in the
      second chip.
      
      PLATFORM_CORE_COUNT macro is set to be multiple of CSS_SGI_CHIP_COUNT
      and topology changes are added to represent the dual-chip configuration.
      
      In order the build the dual-chip platform, CSS_SGI_CHIP_COUNT macro
      should be set to 2:
      export CROSS_COMPILE=<path-to-cross-compiler>
      make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
      
      Change-Id: I576cdaf71f0b0e41b9a9181fa4feb7091f8c7bb4
      Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      Signed-off-by: default avatarVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
      2d4b719c
  4. 06 Feb, 2020 1 commit
    • Max Shvetsov's avatar
      Adds option to read ROTPK from registers for FVP · a6ffddec
      Max Shvetsov authored
      
      
      Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
      Removes hard-coded developer keys. Instead, setting
      ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
      In case of ROT_KEY specified - generates a new hash and replaces the
      original.
      
      Note: Juno board was tested by original feature author and was not tested
      for this patch since we don't have access to the private key. Juno
      implementation was moved to board-specific file without changing
      functionality. It is not known whether byte-swapping is still needed
      for this platform.
      
      Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
      Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
      a6ffddec
  5. 27 Jan, 2020 1 commit
  6. 23 Jul, 2019 1 commit
    • Ambroise Vincent's avatar
      arm: Shorten the Firmware Update (FWU) process · 37b70031
      Ambroise Vincent authored
      
      
      The watchdog is configured with a default value of 256 seconds in order
      to implement the Trusted Board Boot Requirements.
      
      For the FVP and Juno platforms, the FWU process relies on a watchdog
      reset. In order to automate the test of FWU, the length of this process
      needs to be as short as possible. Instead of waiting for those 4 minutes
      to have a reset by the watchdog, tell it to reset immediately.
      
      There are no side effects as the value of the watchdog's load register
      resets to 0xFFFFFFFF.
      
      Tested on Juno.
      
      Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
      Signed-off-by: default avatarAmbroise Vincent <ambroise.vincent@arm.com>
      37b70031
  7. 27 Feb, 2019 1 commit
  8. 19 Feb, 2019 1 commit
  9. 05 Dec, 2018 1 commit
    • Chandni Cherukuri's avatar
      plat/arm/sgi: Use NT_FW_CONFIG instead of HW_CONFIG · 77ab969a
      Chandni Cherukuri authored
      
      
      With the two new APIs 'plat_arm_sgi_get_platform_id' and
      'plat_arm_sgi_get_config_id' that are available now, BL31 need not
      depend on hw_config device tree to identify the platform. In addition
      to this, the existing hardware description in hw_config can be limited
      to use by BL33 and not by the operating system.
      
      So the hardware description from hw_config dts can be moved into
      nt_fw_config dts and the use of hw_config dts can be removed.
      
      Change-Id: I873b7e1e72823d3ec5d253a848e85ae724f09e49
      Signed-off-by: default avatarChandni Cherukuri <chandni.cherukuri@arm.com>
      77ab969a
  10. 03 Dec, 2018 1 commit
    • Chandni Cherukuri's avatar
      plat/arm/sgi: Use platform specific functions to get platform ids · 699223a2
      Chandni Cherukuri authored
      
      
      Add two new functions 'plat_arm_sgi_get_platform_id' and
      'plat_arm_sgi_get_config_id' which will be implemented by all the
      SGI platforms. These functions can be used to determine the part
      number and configuration id of the SGI platforms.
      
      In BL2, these functions are used to populate the 'system-id' node.
      In BL31, these functions are used to populate the 'sgi_plat_info_t'
      structure with the part number and configuration id of the platform.
      
      Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689
      Signed-off-by: default avatarChandni Cherukuri <chandni.cherukuri@arm.com>
      699223a2
  11. 21 Nov, 2018 1 commit
  12. 26 Oct, 2018 1 commit
  13. 18 Oct, 2018 2 commits
  14. 10 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      plat/arm: Move norflash driver to drivers/ folder · aa7877c4
      Antonio Nino Diaz authored
      
      
      This way it can be reused by other platforms if needed.
      
      Note that this driver is designed to work with the Versatile Express NOR
      flash of Juno and FVP. In said platforms, the memory is organized as an
      interleaved memory of two chips with a 16 bit word.
      
      Any platform that wishes to reuse it with a different configuration will
      need to modify the driver so that it is more generic.
      
      Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      aa7877c4
  15. 21 Aug, 2018 1 commit
  16. 28 Mar, 2018 1 commit