- 15 Apr, 2020 1 commit
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Madhukar Pappireddy authored
By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an advisory to the power controller that cluster power is not required when all cores are powered down. The AArch32 CLUSTERPWRDN register is architecturally mapped to the AArch64 CLUSTERPWRDN_EL1 register Change-Id: Ie6e67c1c7d811fa25c51e2e405ca7f59bd20c81b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 07 Apr, 2020 3 commits
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Alexei Fedorov authored
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0. Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Julius Werner authored
This patch adds code to parse memory range information passed by coreboot, and a simple helper to test whether a specific address belongs to a range. This may be useful for coreboot-using platforms that need to know information about the system's memory layout (e.g. to check whether an address passed in via SMC targets valid DRAM). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
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Masahiro Yamada authored
bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3) to check whether the dcache is enabled. Using is_dcache_enabled() is cleaner, and a good abstraction for the library code like this. A problem is is_dcache_enabled() is declared in the local header, lib/xlat_tables_v2/xlat_tables_private.h I searched for a good place to declare this helper. Moving it to arch_helpers.h, closed to cache operation helpers, looks good enough to me. I also changed the type of 'is_cached' to bool for consistency, and to avoid MISRA warnings. Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 06 Apr, 2020 1 commit
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Alexei Fedorov authored
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support. Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 03 Apr, 2020 9 commits
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John Powell authored
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code. Mainly issues like not using boolean expressions in conditionals, conflicting variable names, ignoring return values without (void), adding explicit casts, etc. Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a Signed-off-by: John Powell <john.powell@arm.com>
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Pramod Kumar authored
Present framework restricts platform to pass desired shareability attribute for normal memory region mapped in MMU. it defaults to inner shareability. There are platforms where memories (like SRAM) are not placed at snoopable region in advaned interconnect like CCN/CMN hence snoopable transaction is not possible to these memory. Though These memories could be mapped in MMU as MT_NON_CACHEABLE, data caches benefits won't be available. If these memories are mapped as cacheable with non-shareable attribute, when only one core is running like at boot time, MMU data cached could be used for faster execution. Hence adding support to pass the shareability attribute for memory regions. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754
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Sheetal Tigadoli authored
Add SPI Nor flash support Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Add iproc spi driver Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Add emmc driver for Broadcom platforms Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Change-Id: Icfef5b6923dc292e637001045a334c499d346fe9 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Change-Id: I5daa3f2b4b9d85cb857547a588571a9aa8ad05c2 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: Ic1a392a633b447935fa3a7528326c97845f5b1bc
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Sheetal Tigadoli authored
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: Iabeaee35c22608c93945c8295bf70947b0f6049a
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- 02 Apr, 2020 7 commits
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Sandrine Bailleux authored
The platform io policies array is now always accessed through a fconf getter. This gives us an ideal spot to check for out-of-bound accesses. Remove the assertion in plat_get_image_source(), which is now redundant. Change-Id: Iefe808d530229073b68cbd164d927b8b6662a217 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
The chain of trust array is now always accessed through a fconf getter. This gives us an ideal spot to check for out-of-bound accesses. Change-Id: Ic5ea20e43cf8ca959bb7f9b60de7c0839b390add Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Masahiro Yamada authored
Commit d5e97a1d ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files") does not have commit 848a7e8c ("Build: introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because they were pulled almost at the same time. This is a follow-up conversion to be consistent with commit 11a3c5ee ("plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS"). With this change, the command line option, IMAGE_AT_EL3, will be passed to .S files as well. I remove the definition in include/lib/cpus/aarch64/cpu_macros.S Otherwise, the following error would happen. include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror] Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the .rodata section instead of .bss section. This causes a warning like: /tmp/ccswitLr.s: Assembler messages: /tmp/ccswitLr.s:297: Warning: setting incorrect section attributes for .rodata It is practically no problem, but I want to keep the build log clean. Put the base table into the "base_xlat_table" section to suppress the assembler warnings. The linker script determines its final destination; rodata section if PLAT_RO_XLAT_TABLES=1, or bss section otherwise. So, the result is the same. Change-Id: Ic85d1d2dddd9b5339289fc2378cbcb21dd7db02e Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL and PMF_TIMESTAMP, which previously existed only in BL31. This is not a big deal because unused data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts. I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition. The bss section has bigger alignment. I added BSS_ALIGN for this. Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this change, the BSS symbols in SP_MIN will be sorted by the alignment. This is not a big deal (or, even better in terms of the image size). Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The common section data are repeated in many linker scripts (often twice in each script to support SEPARATE_CODE_AND_RODATA). When you add a new read-only data section, you end up with touching lots of places. After this commit, you will only need to touch bl_common.ld.h when you add a new section to RODATA_COMMON. Replace a series of RO section with RODATA_COMMON, which contains 6 sections, some of which did not exist before. This is not a big deal because unneeded data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts. When I was working on this commit, the BL1 image size increased due to the fconf_populator. Commit c452ba15 ("fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue. I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition. Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
These are mostly used to collect data from special structure, and repeated in many linker scripts. To differentiate the alignment size between aarch32/aarch64, I added a new macro STRUCT_ALIGN. While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional. As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE* are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array data are not populated. Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 01 Apr, 2020 3 commits
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Varun Wadekar authored
This patch changes the prototype cm_setup_context() to use struct entry_point_info rather than the typedef'ed version of it. This fixes the following compilation error seen with EL3_EXCEPTION_HANDLING = 1. <snip> In file included from bl31/ehf.c:19: include/lib/el3_runtime/context_mgmt.h:35:49: error: unknown type name 'entry_point_info_t' 35 | void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep); | ^~~~~~~~~~~~~~~~~~ <snip> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I73b059ff2dade2259cefd0f9a097c7ea4a88055d
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Gilad Ben-Yossef authored
Add Crypto 713 support as crypto module and NVM counter provider. As files under include/drivers/arm/cryptocell/713/ are copied verbatim from the CryptoCell SBROM lib project they are filtered from checkpatch coding style check. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Change-Id: I7c361772f00ca7d96481f81ac6cbb2704467e52c
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Scott Branden authored
Add support to retrieve plat_toc_flags value from FIP header flags. plat_toc_flags is for platform specific use. It is stored in FIP header by fiptool using --plat-toc-flags option. Change-Id: Ibadd91b4f28e6503f4426e4efd404bbe512ad124 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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- 31 Mar, 2020 2 commits
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Masahiro Yamada authored
enable_mmu_* has a different function name, so it is not handy in the shared code. enable_mmu() calls an appropriate one depending on the exception level. Change-Id: I0657968bfcb91c32733f75f9259f550a5c35b1c3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
There are some cases where we want to run EL-dependent code in the shared code. We could use #ifdef, but it leaves slight possibility where we do not know the exception level at the build-time (e.g. library code). The counter approach is to use get_current_el(), but it is run-time detection, so all EL code is linked, some of which might be unneeded. This commit adds get_current_el_maybe_constant(). This is a static inline function that returns a constant value if we know the exception level at build-time. This is mostly the case. if (get_current_el_maybe_constant() == 1) { /* do something for EL1 */ } else if (get_current_el_maybe_constant() == 3) { /* do something for EL3 */ } If get_current_el_maybe_constant() is build-time constant, the compiler will optimize out the unreachable code. If such code is included from the library code, it is not built-time constant. In this case, it falls back to get_current_el(), so it still works. Change-Id: Idb03c20342a5b5173fe2d6b40e1fac7998675ad3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 30 Mar, 2020 1 commit
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Manish V Badarkhe authored
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header and include this header in all ARM platforms. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
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- 25 Mar, 2020 2 commits
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Alexei Fedorov authored
This patch provides support for measured boot by adding calculation of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB. Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Manish V Badarkhe authored
Fixed below 'tautological-constant-compare' error when building the source code with latest clang compiler <clang version 11.0.0>. plat/common/plat_psci_common.c:36:2: error: converting the result of '<<' to a boolean always evaluates to true [-Werror,-Wtautological-constant-compare] PMF_STORE_ENABLE) ^ include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE' PMF_STORE_ENABLE (1 << 0) This error is observed beacuse of CASSERT placed in "PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff: CASSERT(_flags, select_proper_config); where _flags = PMF_STORE_ENABLE (1 << 0) which always results true. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
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- 23 Mar, 2020 1 commit
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Yann Gautier authored
Correct the following warning given by sparse tool: include/drivers/raw_nand.h:158:3: warning: symbol '__packed' was not declared. Should it be static? Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 22 Mar, 2020 1 commit
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Mustafa Yigit Bilgen authored
This patch adds support to handle following TLK SMCs: {TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE} These SMCs need to be supported in ATF in order to forward them to TLK. Otherwise, these functionalities won't work. Brief: TLK_SET_BL_VERSION: This SMC is issued by the bootloader to supply its version to TLK. TLK can use this to prevent rollback attacks. TLK_LOCK_BL_INTERFACE: This SMC is issued by bootloader before handing off execution to the OS. This allows preventing sensitive SMCs being used by the OS. TLK_BL_RPMB_SERVICE: bootloader issues this SMC to sign or verify RPMB frames. Tested by: Tests TLK can receive the new SMCs issued by bootloader Change-Id: I57c2d189a5f7a77cea26c3f8921866f2a6f0f944 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
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- 20 Mar, 2020 1 commit
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Olivier Deprez authored
TPIDR_EL2 is missing from the EL2 state register save/restore sequence. This patch adds it to the context save restore routines. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I35fc5ee82f97b72bcedac57c791312e7b3a45251
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- 19 Mar, 2020 2 commits
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Varun Wadekar authored
TLK does not participate in the system off/reset process and so has no use for the SYSTEM_OFF/RESET notifications. This patch removes the system off/reset handlers as a result. Change-Id: Icf1430b1400cea88000e6d54426eb604a43cbe6c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Kalyani Chidambaram authored
This patch enables dual execution optimized translations for EL2 and EL3 CPU exception levels. Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 17 Mar, 2020 2 commits
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Andre Przywara authored
There is really no reason to use and pass around a struct when its only member is the (fixed) base address. Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically. This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore. Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Manish V Badarkhe authored
Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information: 1. SOC revision 2. SOC version Implementation done using below SMCCC specification document: https://developer.arm.com/docs/den0028/c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b
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- 12 Mar, 2020 1 commit
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Max Shvetsov authored
This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the SPCI component ID as specified in the manifest for secure world requests. Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
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- 11 Mar, 2020 3 commits
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Varun Wadekar authored
This patch adds an interrupt handler for TLK. On receiving an interrupt, the source of the interrupt is determined and the interrupt is marked complete. The IRQ number is passed to TLK along with a special SMC function ID. TLK issues an SMC to notify completion of the interrupt handler in the S-EL1 world. Change-Id: I76f28cee6537245c5e448d2078f86312219cea1a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Madhukar Pappireddy authored
Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN. Created few populator() functions which parse HW_CONFIG device tree and registered them with fconf framework. Many of the changes are only applicable for fvp platform. This patch: 1. Adds necessary symbols and sections in BL31, SP_MIN linker script 2. Adds necessary memory map entry for translation in BL31, SP_MIN 3. Creates an abstraction layer for hardware configuration based on fconf framework 4. Adds necessary changes to build flow (makefiles) 5. Minimal callback to read hw_config dtb for capturing properties related to GIC(interrupt-controller node) 6. updates the fconf documentation Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Madhukar Pappireddy authored
Change-Id: Ie1018bfbae2fe95c699e58648665baa75e862000 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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