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  1. 27 Feb, 2019 5 commits
    • Antonio Nino Diaz's avatar
      BL2: Enable pointer authentication support · 9d93fc2f
      Antonio Nino Diaz authored 
      

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |   +40 |   +0  |   +0  |   +0   |
|                            |  0.2% |       |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           |  +664 |   +0  |  +16  |   +0   |
|                            |  3.1% |       |  0.9% |        |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    SDEI_SUPPORT=1                 \
    EL3_EXCEPTION_HANDLING=1       \
    TSP_NS_INTR_ASYNC_PREEMPT=1    \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

The changes for BL2_AT_EL3 aren't done in this commit.

Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      9d93fc2f
    • Antonio Nino Diaz's avatar
      BL1: Enable pointer authentication support · cd7d6b0e
      Antonio Nino Diaz authored 
      

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |  +108 |  +192 |   +0  |   +0   |
|                            |  0.5% |  0.8% |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           |  +748 |  +192 |  +16  |   +0   |
|                            |  3.7% |  0.8% |  7.0% |        |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    SDEI_SUPPORT=1                 \
    EL3_EXCEPTION_HANDLING=1       \
    TSP_NS_INTR_ASYNC_PREEMPT=1    \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      cd7d6b0e
    • Antonio Nino Diaz's avatar
      Add support for pointer authentication · b86048c4
      Antonio Nino Diaz authored 
      

The previous commit added the infrastructure to load and save
ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
didn't actually enable pointer authentication in the firmware.

This patch adds the functionality needed for platforms to provide
authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
enable pointer authentication in the firmware itself. This option is
disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
enabled.

Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      b86048c4
    • Antonio Nino Diaz's avatar
      Add ARMv8.3-PAuth registers to CPU context · 5283962e
      Antonio Nino Diaz authored 
      

ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.

This feature is supported only in AArch64 state.

This feature is mandatory in ARMv8.3 implementations.

This feature adds several registers to EL1. A new option called
CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
them during Non-secure <-> Secure world switches. This option must be
enabled if the hardware has the registers or the values will be leaked
during world switches.

To prevent leaks, this patch also disables pointer authentication in the
Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
be trapped in EL3.

Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      5283962e
    • Antonio Nino Diaz's avatar
      Cleanup context handling library · 4d1ccf0e
      Antonio Nino Diaz authored 
      

Minor style cleanup.

Change-Id: Ief19dece41a989e2e8157859a265701549f6c585
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      4d1ccf0e
  3. 20 Feb, 2019 1 commit
  5. 19 Feb, 2019 7 commits
  7. 18 Feb, 2019 2 commits
    • Antonio Nino Diaz's avatar
      Disable processor Cycle Counting in Secure state · ed4fc6f0
      Antonio Nino Diaz authored 
      

In a system with ARMv8.5-PMU implemented:

- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
  in Secure state in PMCCNTR.

- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
  Secure state in PMCCNTR_EL0.

So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.

Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      ed4fc6f0
    • Usama Arif's avatar
      Rename PLAT_ARM_BL31_RUN_UART* variable · 0d28096c
      Usama Arif authored 
      

The variable is renamed to PLAT_ARM_RUN_UART as
the UART is used outside BL31 as well.

Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a
Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      0d28096c
  9. 14 Feb, 2019 7 commits
  11. 11 Feb, 2019 2 commits
    • Antonio Nino Diaz's avatar
      cpus: Add casts to all definitions in CPU headers · 1a74e4a8
      Antonio Nino Diaz authored 
      

There are some incorrect casts and some missing casts in the headers.
This patch fixes the ones that were 64-bit or 32-bit wide wrongly and
adds casts where they were missing.

Note that none of the changes of the patch actually changes the values
of the definitions. This patch is just for correctness.

Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      1a74e4a8
    • Antonio Nino Diaz's avatar
      cpus: Fix some incorrect definitions in CPU headers · a69817ed
      Antonio Nino Diaz authored 
      

There are some values that should be 64-bit immediates but that resolve
to 0 because the type of the value is 32-bit wide. This patch casts the
expressions to 64-bit before the shift so that the definition has the
correct value.

The definitions are only used in assembly so far, so the code is not
actually affected by this bug. The assembler treats all values as 64-bit
values, so there are no overflows.

Change-Id: I965e4be631c1d28787c0913661d224c82a6b9155
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      a69817ed
  13. 08 Feb, 2019 2 commits
  15. 06 Feb, 2019 1 commit
  17. 01 Feb, 2019 2 commits
  19. 31 Jan, 2019 3 commits
  21. 30 Jan, 2019 2 commits
    • Antonio Nino Diaz's avatar
      Remove support for the SMC Calling Convention 2.0 · 0709055e
      Antonio Nino Diaz authored 
      This reverts commit 2f370465

 ("Add support for the SMC Calling
Convention 2.0").

SMCCC v2.0 is no longer required for SPM, and won't be needed in the
future. Removing it makes the SMC handling code less complicated.

The SPM implementation based on SPCI and SPRT was using it, but it has
been adapted to SMCCC v1.0.

Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      0709055e
    • Sathees Balya's avatar
      lib/xlat_tables: Add support for ARMv8.4-TTST · cedfa04b
      Sathees Balya authored 
      

ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.

This feature is supported in AArch64 state only.

This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.

Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093
Signed-off-by: default avatarSathees Balya <sathees.balya@arm.com>
      cedfa04b
  23. 25 Jan, 2019 6 commits