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  1. 10 Jul, 2020 1 commit
    • Jacky Bai's avatar
      plat: imx8m: Move the gpc hw reg to a separate header file · 9e5c3e92
      Jacky Bai authored 
      

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some slight difference, so move the hw reg
offset & most of the bitfield defines in 'gpc_reg.h' that
is specific to each SoC.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f
      9e5c3e92
  3. 06 Jul, 2020 1 commit
    • Abdellatif El Khlifi's avatar
      corstone700: splitting the platform support into FVP and FPGA · ef93cfa3
      Abdellatif El Khlifi authored 
      

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

  fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
  - Enabling NEED_BL33 option
  - Fixing non-secure image base: For no preloaded bl33 we want to
    have the NS base set on shared ram. Setup a memory map region
    for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: default avatarRui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      ef93cfa3
  5. 29 Jun, 2020 2 commits
  7. 26 Jun, 2020 2 commits
    • Andre Przywara's avatar
      arm_fpga: Fix MPIDR topology checks · 53baf7f0
      Andre Przywara authored 
      

The plat_core_pos_by_mpidr() implementation for the Arm FPGA port has
some issues, which leads to problems when matching GICv3 redistributors
with cores:
- The power domain tree was not taking multithreading into account, so
  we ended up with the wrong mapping between MPIDRs and core IDs.
- Before even considering an MPIDR, we try to make sure Aff2 is 0.
  Unfortunately this is the cluster ID when the MT bit is set.
- We mask off the MT bit in MPIDR, before basing decisions on it.
- When detecting the MT bit, we are properly calculating the thread ID,
  but don't account for the shift in the core and cluster ID checks.

Those problems lead to early rejections of MPIDRs values, in particular
when called from the GIC code. As a result, CPU_ON for secondary cores
was failing for most of the cores.

Fix this by properly handling the MT bit in plat_core_pos_by_mpidr(),
also pulling in FPGA_MAX_PE_PER_CPU when populating the power domain
tree.

Change-Id: I71b2255fc0d27bfe5806511df479ab38e4e33fc4
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      53baf7f0
    • Manish V Badarkhe's avatar
      plat/arm: Use only fw_config between bl2 and bl31 · 7fb9bcd8
      Manish V Badarkhe authored 
      

Passed the address of fw_config instead of soc_fw_config
as arg1 to BL31 from BL2 for ARM fvp platform.

BL31 then retrieve load-address of other device trees
from fw_config device tree.
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib7e9581cd765d76111dcc3b7e0dafc12503c83c1
      7fb9bcd8
  9. 25 Jun, 2020 2 commits
    • Manish V Badarkhe's avatar
      plat/arm: Increase size of firmware configuration area · ce4ca1a8
      Manish V Badarkhe authored 
      

Increased the size of firmware configuration area to accommodate
all configs.

Updated maximum size of following bootloaders due to increase
in firmware configs size and addition of the code in the BL2.

1. Increased maximum size of BL2 for Juno platform in no
   optimisation case.
2. Reduced maximum size of BL31 for fvp and Juno platform.
3. Reduced maximum size of BL32 for Juno platform.

Change-Id: Ifba0564df0d1fe86175bed9fae87fdcf013b1831
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      ce4ca1a8
    • Manish V Badarkhe's avatar
      plat/arm: Load and populate fw_config and tb_fw_config · 82869675
      Manish V Badarkhe authored 
      

Modified the code to do below changes:

1. Load tb_fw_config along with fw_config by BL1.
2. Populate fw_config device tree information in the
   BL1 to load tb_fw_config.
3. In BL2, populate fw_config information to retrieve
   the address of tb_fw_config and then tb_fw_config
   gets populated using retrieved address.
4. Avoid processing of configuration file in case of error
   value returned from "fw_config_load" function.
5. Updated entrypoint information for BL2 image so
   that it's arg0 should point to fw_config address.
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
Change-Id: Ife6f7b673a074e7f544ee3d1bda7645fd5b2886c
      82869675
  11. 24 Jun, 2020 6 commits
  13. 23 Jun, 2020 9 commits
  15. 21 Jun, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: sanity check NS address and size before use · 685e5609
      Varun Wadekar authored 
      

This patch updates the 'bl31_check_ns_address()' helper function to
check that the memory address and size passed by the NS world are not
zero.

The helper fucntion also returns the error code as soon as it detects
inconsistencies, to avoid multiple error paths from kicking in for the
same input parameters.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>

Change-Id: I46264f913954614bedcbde12e47ea0c70cd19be0
      685e5609
  17. 19 Jun, 2020 13 commits
  19. 18 Jun, 2020 1 commit
    • Marcin Wojtas's avatar
      plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs · b5c850d4
      Marcin Wojtas authored 
      

The Marvell Armada 37xx SoCs-based platforms contain a bit
awkward directory structure because the currently only one
supported PLAT and PLAT_FAMILY are the same. Modify the latter
to 'a3k' in order to improve it and keep plat/marvell/armada
tree more consistent:

plat/marvell/
├── armada
│   ├── a3k
│   │   ├── a3700

[...]

│   ├── a8k
│   │   ├── a70x0

[...]

Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a
Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
      b5c850d4
  21. 17 Jun, 2020 1 commit
    • Manish V Badarkhe's avatar
      plat/arm: Fix load address of TB_FW_CONFIG · 15865870
      Manish V Badarkhe authored 
      

Load address of tb_fw_config is incorrectly mentioned
in below device trees:
1. rdn1edge_fw_config.dts
2. tc0_fw_config.dts

Till now, tb_fw_config load-address is not being retrieved from
device tree and hence never exeprienced any issue for tc0 and
rdn1edge platform.

For tc0 and rdn1edge platform, Load-address of tb_fw_config should
be the SRAM base address + 0x300 (size of fw_config device tree)
Hence updated these platform's fw_config.dts accordingly to reflect
this load address change.

Change-Id: I2ef8b05d49be10767db31384329f516df11ca817
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      15865870
  23. 12 Jun, 2020 1 commit