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We now have code to detect the CPU topology at runtime, and can also
populate the CPU nodes in a devicetree accordingly. This is used by the
ARM FPGA port, for instance.
But also a GICv3 compatible interrupt controller provides MMIO frames
per core, so the size of this region needs to be adjusted in the DT,
to match the number of cores as well.

Provide a generic function to find the GICv3 interrupt controller in
the DT, then adjust the "reg" entry to match the number of detected
cores. Since the size of the GICR frame per cores differs between
GICv4 and GICv3, this size is supplied as a parameter to the function.
The caller should determine the applicable value by either hardcoding
it or by observing GICR_TYPER.VLPIS.

Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

* changes:
  clk: stm32mp1: fix rcc mckprot status
  drivers: st: add missing includes in ETZPC header
  mmc: st: clear some flags before sending a command
  mmc: st: correct retries management
  nand: raw_nand: fix timeout issue in nand_wait_ready
  mtd: spi_nor: change message level on macronix detection
  gpio: stm32_gpio: check GPIO node status after checking DT
  crypto: stm32_hash: fix issue when restarting computation

* changes:
  plat: tc0: enable TZC
  fdts: tc0: update MHUv2 interrupt number

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the flash memory used for the mem_protect region was not
mapped. This results in a crash when an OS calls PSCI MEM_PROTECT.

To fix this map the flash region used for mem_protect.

Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

Merge "Select the Log Level for the Event Log Dump on Measured Boot at build time." into integration

Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc
Signed-off-by: Usama Arif <usama.arif@arm.com>

MCKPROT hardening in RCC mandates that both bits RCC[TZEN] and
RCC[MCKPROT] are enabled. This change fixes stm32mp1_rcc_is_mckprot()
to check both bits, not RCC[MCKPROT] only.

This change also updates stm32mp1_rcc_is_secure() for consistency.

Change-Id: If1f07babdcb5677906ddbf974d9dc17255d4e174
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Depending on compiler, the issue about bool or uint*_t not defined can
appear.
Correct this by adding stdbool.h and stdint.h includes in etzpc.h.

Change-Id: If1419dc511efbe682459fa4a776481fa52a38aa3
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The ICR static flags are cleared before sending a command.
The SDMMC_DCTRLR register is set to 0 if no data is expected on a given
command or on the next command in case of CMD55.

Change-Id: I5ae172a484218f53160e98b3684967c6960475a6
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The retries number should be 3.
A warning message is added in mmc_block_read(), and the code is refactored.

Change-Id: I577c7dd91c451c7580b1660042cb5fe26ee3fa12
Signed-off-by: Yann Gautier <yann.gautier@st.com>

nand_wait_ready is called with a millisecond delay
but the timeout used a micro second. Fixing the conversion
in the timeout call.
The prototype of the function is also changed to use an unsigned int
parameter.

Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Change the detection message from WARN to INFO when macronix
NOR is detected.

Change-Id: I488696f1fb75b823e85decfcd6cd32e7b36a6c2e
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The call to fdt_get_status(node) has to be done after the DT is found
to be valid.

Fixes: 1fc2130c

 stm32mp1: update device tree and gpio functions

Change-Id: I70f803aae3dde128a9e740f54c8837b64cb1a244
Signed-off-by: Yann Gautier <yann.gautier@st.com>

While restarting a new hash computation, STR register
is not cleared. It needs to be written before each
computation.

Change-Id: If65902dd21f9c139ec5da3ca87721232f73710db
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

This is as part of the architecture change in TC0.

Change-Id: I470241f67938e7998941d26f0e8bc05073234152
Signed-off-by: Usama Arif <usama.arif@arm.com>

Builds in Debug mode with Measured Boot enabled might run out of trusted
SRAM. This patch allows to change the Log Level at which the Measured Boot
driver will dump the event log, so the latter can be accessed even on
Release builds if necessary, saving space on RAM.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I133689e313776cb3f231b774c26cbca4760fa120

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I991f653a7ace04f9c84bcda78ad8d7114ea18e93
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

* changes:
  plat: tegra: Use generic ehf defines
  ehf: use common priority level enumuration

Remote chip  ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.

Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>

* changes:
  plat/arm: fvp: Increase BL2 maximum size
  lib: fconf: Implement a parser to populate CoT

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
number of PEs (pinned MP). Adjust the SPMC manifest such that the
number of ECs is equal to the number of PEs.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/


secure-partition-manager.html#platform-topology
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie8c7d96ae7107cb27f5b97882d8f476c18e026d4

Increased BL2 maximum size when CoT descriptors are placed
in device tree.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e189e7f15eb4f1a8db070542893cb5b

Implemented a parser which populates the properties of
the CoT descriptors as per the binding document [1].
'COT_DESC_IN_DTB' build option is disabled by default and can
be enabled in future for all Arm platforms by making necessary
changes in the memory map.
Currently, this parser is tested only for FVP platform.

[1]:
https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html



Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

* changes:
  Update makefile to build fiptool for Windows
  Fix fiptool packaging issue on windows

Change-Id: Iedaa83ed546eb2476849a8d53f6e05b847a48b23
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>