- 05 Dec, 2016 4 commits
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dp-arm authored
Change-Id: Ie3e43e9f7d31df40a5997047b9bddec0a06fd47f Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
Change-Id: I18a4327e41fc090dcea9a647f7673182ca0ed1d9 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
Change-Id: I62c1a636eb0d9f73fa3a6356e32b5a44f268d421 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
Additionally, remove the -o option for the create command as it is not supported. Change-Id: I27993a6fc5e3b0b9710e2ec5322e4296bc87d0df Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 30 Nov, 2016 1 commit
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davidcunado-arm authored
Fix normal memory bakery lock implementation
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- 25 Nov, 2016 1 commit
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davidcunado-arm authored
rk3399: Add CFI debug information to SRAM functions
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- 24 Nov, 2016 1 commit
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Soren Brinkmann authored
Commit b91d935f ("Add CFI debug frame information for ASM functions") modifies the assembly macros 'func' and 'endfunc' to include CFI debug frame information. The rockchip platform uses a custom version of the 'func' macro with the common 'endfunc' macro. The custom macro wasn't updated in b91d935f resulting in the following build error: plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S: Assembler messages: plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S:155: Error: .cfi_endproc without corresponding .cfi_startproc Makefile:532: recipe for target 'build/rk3399/release/bl31/plat_helpers.o' failed make: *** [build/rk3399/release/bl31/plat_helpers.o] Error 1 Fixing this by updating the sram_func macro in the rk3399 port. Fixes: b91d935f ("Add CFI debug frame information for ASM functions") Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 23 Nov, 2016 4 commits
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danh-arm authored
Add CFI debug frame information for ASM functions
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danh-arm authored
Minor fixes in the Trusty SPD code
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Sandrine Bailleux authored
This patch fixes the following coding style error reported by the checkpatch.pl script: Bad function definition - void el3_exit() should probably be void el3_exit(void) There is another one but it's a false positive so there's no point in fixing it: space prohibited after that '&' (ctx:WxW) +#define SMC_NR(entity, fn, fastcall, smc64) ((((fastcall) & 0x1) << 31) | \ ^ Change-Id: I34de0337c7216dabd16395879f13845a60ee6df0 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
In release builds, the Trusty SPD fails to build because of an unused variable. Note that this warning message doesn't show in debug builds because INFO() messages are not compiled out like in release mode. This patch fixes this issue by removing this variable and using its value in place directly in the INFO() macro call. Change-Id: I1f552421181a09412315eef4eaca586012022018 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 22 Nov, 2016 4 commits
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danh-arm authored
Clarify dependency for PSCI_EXTENDED_STATE_ID
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danh-arm authored
ZynqMP Updates
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danh-arm authored
spd: dispatcher for interacting with the Trusty TEE
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Douglas Raillard authored
Add dependency information in the user guide for ARM_RECOM_STATE_ID_ENC that needs to be set when using PSCI_EXTENDED_STATE_ID on ARM platforms. Also clarify the build error message. Change-Id: Id125a0299b179f5f222bca4e2503204bf89a3c59 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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- 21 Nov, 2016 4 commits
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Soby Mathew authored
This patch fixes an issue in the normal memory bakery lock implementation. During assertion of lock status, there is a possibility that the assertion could fail. This is because the previous update done to the lock status by the owning CPU when not participating in cache coherency could result in stale data in the cache due to cache maintenance operations not propagating to all the caches. This patch fixes this issue by doing an extra read cache maintenance operation prior to the assertion. Fixes ARM-software/tf-issues#402 Change-Id: I0f38a7c52476a4f58e17ebe0141d256d198be88d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Douglas Raillard authored
This allows the debugger to print the callstack when there is an assembly function in the callstack. It will work as long as the CFA pointer (frame pointer) location is not modified (i.e. x29 is not touched in AArch64 state). It is the case in almost all assembly functions, so this patch improves the average debugging experience. Call stacks from the debugger should still be interpreted with care. In more complex functions, one could use .cfi* directives to inform the debugger about the new location of the CFA pointer. Change-Id: I9dabfbc033b45e8528e67f4823c17de7bf02fa24 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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danh-arm authored
Cosmetic change to exception table
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danh-arm authored
Docs: Clarify IRQ/FIQ handler API in Interrupt Design Guide
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- 17 Nov, 2016 1 commit
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Douglas Raillard authored
The API description currently states that interrupt handlers (interrupt_type_handler_t pointers) SHOULD return a pointer to the target cpu_context. This patch rewords the description of the interrupts handlers to state that it MUST return a pointer to the target security context. It also warns about potential portability issue. Specifically, this pointer is not used on AArch64 and calls to context library APIs must be used to ask BL31 to return to a specific context. However, this could change in the future and interrupt handlers must always return the pointer. Change-Id: I3f82a046de4d7a5b51a8cbebe7eb2a00dbbdb4f0 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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- 16 Nov, 2016 12 commits
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Soren Brinkmann authored
The callback IRQ is delivered to the NS OS. Provide an interface to allow the NS OS to obtain the callback data from the secure HW. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
The IPI hardware is secure and managed by ATF, nevertheless we deliver the IRQ to the rich OS. The IRQ is needed to receive PM callbacks. Enable the IPI interrupt when the rich OS probes the API version. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
Remove dead code pieces and stale comments. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
Cc: Michal Simek <michal.simek@xilinx.com> Reported-by: Jonas Karlsson <jonas.karlsson@atero.se> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Soren Brinkmann authored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
Use the PMUFW get_chipid call to obtain IDCODE and version register. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
Allow reading more than just a single value from the message buffer. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
On ZynqMP the FSBL will configure the system counter. Hence, remove the initialization of the system counter with hardcoded values from the ATF and use the setup provided by the bootloader. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Soren Brinkmann authored
The silicon ID does not change at runtime. Skip the IO access if the ID has been read before. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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danh-arm authored
Document plat_psci_ops.(system_off|system_reset)
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danh-arm authored
firmware-design.md: Fix broken link
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danh-arm authored
Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR
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- 14 Nov, 2016 3 commits
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Douglas Raillard authored
* Move comments on unhandled exceptions at the right place. * Reformat the existing comments to highlight the start of each block of 4 entries in the exception table to ease navigation (lines of dash reserved for head comments). * Reflow comments to 80 columns. Change-Id: I5ab88a93d0628af8e151852cb5b597eb34437677 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Douglas Raillard authored
Fix a link broken by a missing space that turned it into a link to an non-existent anchor. Change-Id: Ie863e963db28afa3a28b69d3f63bd7638bdf5af9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Douglas Raillard authored
fixes ARM-Software/tf-issues#346 Change-Id: I946c8eab650bba7407775462ce91f394d767e079 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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- 09 Nov, 2016 3 commits
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David Cunado authored
In order to avoid unexpected traps into EL3/MON mode, this patch resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64, and SDCR and HDCR for AArch32. MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the start of BL1 and BL31/SMP_MIN. For MDCR_EL2/HDCR, this patch zero's the bits that are architecturally UNKNOWN values on reset. This is done when exiting from EL3/MON mode but only on platforms that support EL2/HYP mode but choose to exit to EL1/SVC mode. Fixes ARM-software/tf-issues#430 Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6 Signed-off-by: David Cunado <david.cunado@arm.com>
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danh-arm authored
readme.md: Add tested Linaro release information for FVPs
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Douglas Raillard authored
The platform testing information in the readme currently states which Linaro release has been tested on Juno platform. This patch adds the same information for the AArch64/32 FVPs platforms. Change-Id: Ifa89843ee1744e5030367197648b7a2f4c44cc24 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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- 08 Nov, 2016 2 commits
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Varun Wadekar authored
This patch adds the secure payload dispatcher for interacting with Google's Trusty TEE. Documentation for Trusty can be found at https://source.android.com/security/trusty Original authors: ----------------- * Arve Hjønnevåg <arve@android.com> * Michael Ryleev <gmar@google.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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danh-arm authored
rk3399: fixes and updates for s2r
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