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  1. 27 Apr, 2021 5 commits
    • Manish V Badarkhe's avatar
      fix(driver/auth): avoid NV counter upgrade without certificate validation · a2a5a945
      Manish V Badarkhe authored 
      

Platform NV counter get updated (if cert NV counter > plat NV counter)
before authenticating the certificate if the platform specifies NV
counter method before signature authentication in its CoT, and this
provides an opportunity for a tempered certificate to upgrade the
platform NV counter. This is theoretical issue, as in practice none
of the standard CoT (TBBR, dualroot) or upstream platforms ones (NXP)
exercised this issue.

To fix this issue, modified the auth_nvctr method to do only NV
counter check, and flags if the NV counter upgrade is needed or not.
Then ensured that the platform NV counter gets upgraded with the NV
counter value from the certificate only after that certificate gets
authenticated.

This change is verified manually by modifying the CoT that specifies
certificate with:
1. NV counter authentication before signature authentication
   method
2. NV counter authentication method only

Change-Id: I1ad17f1a911fb1035a1a60976cc26b2965b05166
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      a2a5a945
    • Manish Pandey's avatar
      Merge changes from topic "rd_plat_variants" into integration · d3555651
      Manish Pandey authored 
      * changes:
  feat(board/rdn2): add support for variant 1 of rd-n2 platform
  feat(plat/sgi): introduce platform variant build option
      d3555651
    • Aditya Angadi's avatar
      feat(board/rdn2): add support for variant 1 of rd-n2 platform · fe5d5bbf
      Aditya Angadi authored 
      

Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a
variant of RD-N2 platform with a reduced interconnect mesh size (3x3)
and core count (8-cores). Its platform variant id is 1.

Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      fe5d5bbf
    • Aditya Angadi's avatar
      feat(plat/sgi): introduce platform variant build option · cfe1506e
      Aditya Angadi authored 
      

A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.

An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1

Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      cfe1506e
    • Manish Pandey's avatar
      Merge changes I36e45c0a,I69c21293 into integration · 81579422
      Manish Pandey authored 
      * changes:
  plat/qemu: add "max" cpu support
  Add support for QEMU "max" CPU
      81579422
  3. 26 Apr, 2021 5 commits
  5. 23 Apr, 2021 16 commits
  7. 22 Apr, 2021 7 commits
  9. 21 Apr, 2021 7 commits
    • Mark Dykes's avatar
      Merge "Add documentation for SMMUv3 driver in Hafnium(SPM)" into integration · 1d1e5006
      Mark Dykes authored
      1d1e5006
    • bipin.ravi's avatar
      Merge "Add "_arm" suffix to Makalu ELP CPU lib" into integration · dfe64665
      bipin.ravi authored
      dfe64665
    • Manish Pandey's avatar
      Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration · e9cd36f5
      Manish Pandey authored 
      * changes:
  renesas: rzg: Add support to identify EK874 RZ/G2E board
  drivers: renesas: common: watchdog: Add support for RZ/G2E
  drivers: renesas: rzg: Add QoS support for RZ/G2E
  drivers: renesas: rzg: Add PFC support for RZ/G2E
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2N
  drivers: renesas: rzg: Add PFC support for RZ/G2N
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2H
  drivers: renesas: rzg: Add PFC support for RZ/G2H
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
  drivers: renesas: rzg: Switch using common ddr code
  drivers: renesas: ddr: Move to common
      e9cd36f5
    • Manish Pandey's avatar
      Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration · d8dc8c9e
      Manish Pandey authored
      d8dc8c9e
    • Alexei Fedorov's avatar
      Plat FVP: Fix Generic Timer interrupt types · dfa6c540
      Alexei Fedorov authored 
      

The Arm Generic Timer specification mandates that the
interrupt associated with each timer is low level triggered,
see:

Arm Cortex-A76 Core:
"Each timer provides an active-LOW interrupt output to the SoC."

Arm Cortex-A53 MPCore Processor:
"It generates timer events as active-LOW interrupt outputs and
event streams."

The following files in fdts\

fvp-base-gicv3-psci-common.dtsi
fvp-base-gicv3-psci-aarch32-common.dtsi
fvp-base-gicv2-psci-aarch32.dts
fvp-base-gicv2-psci.dts
fvp-foundation-gicv2-psci.dts
fvp-foundation-gicv3-psci.dts

describe interrupt types as edge rising
IRQ_TYPE_EDGE_RISING = 0x01:

interrupts = <1 13 0xff01>,
             <1 14 0xff01>,
             <1 11 0xff01>,
             <1 10 0xff01>;

, see include\dt-bindings\interrupt-controller\arm-gic.h:

which causes Linux to generate the warnings below:
arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low
arch_timer: WARNING: Please fix your firmware

This patch adds GIC_CPU_MASK_RAW macro definition to
include\dt-bindings\interrupt-controller\arm-gic.h,
modifies interrupt type to IRQ_TYPE_LEVEL_LOW and
makes use of type definitions in arm-gic.h.

Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      dfa6c540
    • Manish Pandey's avatar
      Merge changes I3c25c715,I6d30b081 into integration · 617632bf
      Manish Pandey authored 
      * changes:
  plat: xilinx: versal: Add the IPI CRC checksum macro support
  plat: xilinx: common: Rename the IPI CRC checksum macro
      617632bf
    • Joanna Farley's avatar
      Merge changes from topic "ck/conventional-commits" into integration · 745df305
      Joanna Farley authored 
      * changes:
  build(hooks): add commitlint hook
  build(hooks): add Commitizen hook
  build(hooks): add Gerrit hook
  build(hooks): add Husky configuration
      745df305