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Default board configuration was set to bcm958742k which is not present
in current codebase. This causes a default platform build to fail.
Changing to bcm958742t.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ie24f94ef0ef316ff56fe142df5de45d70ba93c28

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.

Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>

with commit a6ea06f5

, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fpga platform.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic5ccae842b39b7db06d4f23c5738b174c42edf63

Merge "xlat lib v2: Add support to pass shareability attribute for normal memory region" into integration

* changes:
  doc: brcm: Add documentation file for brcm stingray platform
  drivers: Add SPI Nor flash support
  drivers: Add iproc spi driver
  drivers: Add emmc driver for Broadcom platforms
  Add BL31 support for Broadcom stingray platform
  Add BL2 support for Broadcom stingray platform
  Add bl31 support common across Broadcom platforms
  Add bl2 setup code common across Broadcom platforms
  drivers: Add support to retrieve plat_toc_flags

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. it defaults to inner shareability.

There are platforms where memories (like SRAM) are not placed at snoopable
region in advaned interconnect like CCN/CMN hence snoopable transaction is
not possible to these memory. Though These memories could be mapped in MMU
as MT_NON_CACHEABLE, data caches benefits won't be available.

If these memories are mapped as cacheable with non-shareable attribute,
when only one core is running like at boot time, MMU data cached could be
used for faster execution. Hence adding support to pass the shareability
attribute for memory regions.
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: I5e2c1220e9694d6ba771cc90daa0e70e967eebe6

Add SPI Nor flash support

Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Add iproc spi driver

Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Add emmc driver for Broadcom platforms

Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Change-Id: Icfef5b6923dc292e637001045a334c499d346fe9
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Change-Id: I5daa3f2b4b9d85cb857547a588571a9aa8ad05c2
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Ic1a392a633b447935fa3a7528326c97845f5b1bc

* changes:
  Check for out-of-bound accesses in the platform io policies
  Check for out-of-bound accesses in the CoT description

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Iabeaee35c22608c93945c8295bf70947b0f6049a

Using get_current_el_maybe_constant() produces more optimized code
because in most cases, we know the exception level at build-time.
For example, BL31 runs at EL3, so unneeded code will be trimmed.

[before]

0000000000000000 <is_dcache_enabled>:
   0:   d5384240        mrs     x0, currentel
   4:   53020c00        ubfx    w0, w0, #2, #2
   8:   7100041f        cmp     w0, #0x1
   c:   54000081        b.ne    1c <is_dcache_enabled+0x1c>  // b.any
  10:   d5381000        mrs     x0, sctlr_el1
  14:   53020800        ubfx    w0, w0, #2, #1
  18:   d65f03c0        ret
  1c:   7100081f        cmp     w0, #0x2
  20:   54000061        b.ne    2c <is_dcache_enabled+0x2c>  // b.any
  24:   d53c1000        mrs     x0, sctlr_el2
  28:   17fffffb        b       14 <is_dcache_enabled+0x14>
  2c:   d53e1000        mrs     x0, sctlr_el3
  30:   17fffff9        b       14 <is_dcache_enabled+0x14>

[after]

0000000000000000 <is_dcache_enabled>:
   0:   d53e1000        mrs     x0, sctlr_el3
   4:   53020800        ubfx    w0, w0, #2, #1
   8:   d65f03c0        ret

Change-Id: I3698fae9b517022ff9fbfd4cad3a320c6e137e10
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

* changes:
  plat: remove redundant =1 from -D option
  Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS

The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Remove the assertion in plat_get_image_source(), which is now redundant.

Change-Id: Iefe808d530229073b68cbd164d927b8b6662a217
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

The chain of trust array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Change-Id: Ic5ea20e43cf8ca959bb7f9b60de7c0839b390add
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I397b642eff8a09b201f497f8d2ba39e2460c0dba

* changes:
  xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES
  linker_script: move bss section to bl_common.ld.h
  linker_script: replace common read-only data with RODATA_COMMON
  linker_script: move more common code to bl_common.ld.h

Submitting a change for review using 'git review' will now automatically use
the special refs/for/integration ref (instead of targeting the master
branch).

Change-Id: Idef58b20c492bf5ab06599f4cd4a5e5b75837066
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This is not used in BL31 or Bl32 for this platform.

Pass it to BL2_CPPFLAGS instead of defining it for all BL images.

This will produce slightly smaller BL31 and Bl32.

Change-Id: I66ec5179f8dc5b112e65547335e7dd0a0f4074cd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.

  -D <name>
      Predefine <name> as a macro, with definition 1.

The same applied with Clang, too.

In the context of -D option, =1 is always redundant.

Change-Id: I487489a1ea3eb51e734741619c1e65dab1420bc4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Commit d5e97a1d ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3
globally for C files") does not have commit 848a7e8c ("Build:
introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because
they were pulled almost at the same time.

This is a follow-up conversion to be consistent with commit
11a3c5ee

 ("plat: pass -D option to BL*_CPPFLAGS instead of
BL*_CFLAGS").

With this change, the command line option, IMAGE_AT_EL3, will be
passed to .S files as well.

I remove the definition in include/lib/cpus/aarch64/cpu_macros.S

Otherwise, the following error would happen.

  include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror]

Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the
.rodata section instead of .bss section.

This causes a warning like:

/tmp/ccswitLr.s: Assembler messages:
/tmp/ccswitLr.s:297: Warning: setting incorrect section attributes for .rodata

It is practically no problem, but I want to keep the build log clean.

Put the base table into the "base_xlat_table" section to suppress the
assembler warnings.

The linker script determines its final destination; rodata section if
PLAT_RO_XLAT_TABLES=1, or bss section otherwise. So, the result is the
same.

Change-Id: Ic85d1d2dddd9b5339289fc2378cbcb21dd7db02e
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL
and PMF_TIMESTAMP, which previously existed only in BL31. This is not
a big deal because unused data should not be compiled in the first
place. I believe this should be controlled by BL*_SOURCES in Makefiles,
not by linker scripts.

I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more  unexpected
code addition.

The bss section has bigger alignment. I added BSS_ALIGN for this.

Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this
change, the BSS symbols in SP_MIN will be sorted by the alignment.
This is not a big deal (or, even better in terms of the image size).

Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The common section data are repeated in many linker scripts (often
twice in each script to support SEPARATE_CODE_AND_RODATA). When you
add a new read-only data section, you end up with touching lots of
places.

After this commit, you will only need to touch bl_common.ld.h when
you add a new section to RODATA_COMMON.

Replace a series of RO section with RODATA_COMMON, which contains
6 sections, some of which did not exist before.

This is not a big deal because unneeded data should not be compiled
in the first place. I believe this should be controlled by BL*_SOURCES
in Makefiles, not by linker scripts.

When I was working on this commit, the BL1 image size increased
due to the fconf_populator. Commit c452ba15

 ("fconf: exclude
fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue.

I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more  unexpected
code addition.

Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

These are mostly used to collect data from special structure,
and repeated in many linker scripts.

To differentiate the alignment size between aarch32/aarch64, I added
a new macro STRUCT_ALIGN.

While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional.
As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE*
are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array
data are not populated.

Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.

Verified that the watchdog timer interrupt fires after migrating to
the EHF.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5

This patch changes the prototype cm_setup_context() to use struct entry_point_info
rather than the typedef'ed version of it. This fixes the following compilation error
seen with EL3_EXCEPTION_HANDLING = 1.

<snip>
In file included from bl31/ehf.c:19:
include/lib/el3_runtime/context_mgmt.h:35:49: error: unknown type name 'entry_point_info_t'
   35 | void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep);
      |                                                 ^~~~~~~~~~~~~~~~~~
<snip>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I73b059ff2dade2259cefd0f9a097c7ea4a88055d