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The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every board), but it is inconsistent.

Add the respective enable bits for those two rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
  register 0x8f. It is 0 by default, but rebooting from Linux might have
  left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
  actually drive power to it. This is done via bit 2 in register 0x30.

Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.

Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.

Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The legacy Allwinner ATF port used to setup some clocks, and U-Boot is
still relying on this. We don't need to setup the full set, as the SPL
is doing most of it, but it misses one clock (AHB2) and programs another
(AHB1) to quite conservative values.

Fix this up during the platform setup to improve USB and Ethernet
performance, iperf values go up by 31% in my setup with that patch.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Correct some issues found with static analysis tools

cadence: uart: comply to console_register prototype

Signed-off-by: Alexei Colin <acolin@isi.edu>

hikey, hikey960, poplar: use new console APIs

Add support new Xilinx Versal ACAP platform

It is already in include/drivers/st/stm32mp1_ddr_helpers.h.
Signed-off-by: Yann Gautier <yann.gautier@st.com>

These issues wer found by sparse:

drivers/st/clk/stm32mp1_clk.c:1524:19:
 warning: incorrect type in assignment (different base types)
    expected restricted fdt32_t const [usertype] *pkcs_cell
    got unsigned int const [usertype] *

plat/st/stm32mp1/plat_image_load.c:13:6:
 warning: symbol 'plat_flush_next_bl_params' was not declared.
 Should it be static?
plat/st/stm32mp1/plat_image_load.c:21:16:
 warning: symbol 'plat_get_bl_image_load_info' was not declared.
 Should it be static?
plat/st/stm32mp1/plat_image_load.c:29:13:
 warning: symbol 'plat_get_next_bl_params' was not declared.
 Should it be static?

plat/st/stm32mp1/bl2_io_storage.c:40:10:
 warning: symbol 'block_buffer' was not declared. Should it be static?
Signed-off-by: Yann Gautier <yann.gautier@st.com>

cppcheck:
[drivers/partition/gpt.c:19] -> [drivers/partition/gpt.c:19]:
 (warning) Either the condition 'str_in!=((void*)0)' is redundant
 or there is possible null pointer dereference: name.

sparse:
drivers/partition/gpt.c:39:9:
 warning: Using plain integer as NULL pointer
Signed-off-by: Yann Gautier <yann.gautier@st.com>

These warnings were issued by sparse:
plat/st/stm32mp1/stm32mp1_pm.c:365:36:
 warning: incorrect type in initializer (different modifiers)
    expected void ( *[noreturn] pwr_domain_pwr_down_wfi )( ... )
    got void ( [noreturn] *<noident> )( ... )
plat/st/stm32mp1/stm32mp1_pm.c:366:23:
 warning: incorrect type in initializer (different modifiers)
    expected void ( *[noreturn] system_off )( ... )
    got void ( [noreturn] *<noident> )( ... )
plat/st/stm32mp1/stm32mp1_pm.c:367:25:
 warning: incorrect type in initializer (different modifiers)
    expected void ( *[noreturn] system_reset )( ... )
    got void ( [noreturn] *<noident> )( ... )

This cannot be changed the other way in all platforms pm drivers
or else there is a compilation error:
plat/st/stm32mp1/stm32mp1_pm.c:234:1: error: attributes should be specified
 before the declarator in a function definition
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.

This patch adds Virtual QEMU platform support for
this SoC "versal_virt".
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Arm platforms: Fix DRAM address macros

rcar_gen3: E3 target: fix compilation issues

plat/arm: Fix MISRA defects in common code

Remove unneeded _tzc_get_max_top_addr() function

plat/arm: Support direct Linux kernel boot in AArch32

On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently
32-bit values (because they are suffixed with UL and the value
0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When
summing them up, the result overflows the maximum value that can be
encoded in a 32-bit value so it wraps around and does not result in
the expected value.

This patch changes the suffix of these constants into ULL so that they
always are 64-bit values.

Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This function was needed at the time where we didn't have the
compiler_rt lib. An AArch32-specific variant was provided to handle
the 64-bit shift operation in 32-bit. This is no longer needed.

Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __aeabi_llsr() builtin, which is required by a
subsequent patch that uses a logical right shift operator in AArch32.

Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Introduce new fdt helpers

Target builds but has not been tested.
Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>

Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>

hikey: add delay after eMMC initialized

This option allows the Trusted Firmware to directly jump to Linux
kernel for aarch32 without the need of an intermediate loader such
as U-Boot.

Similar to AArch64 ARM_LINUX_KERNEL_AS_BL33 only available with
RESET_TO_SP_MIN=1 as well as BL33 and DTB are preloaded in memory.

Change-Id: I908bc1633696be1caad0ce2f099c34215c8e0633
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

fdtw_read_cells() can only read one or two cells, sometimes it may be
needed to read more cells from one property.

Change-Id: Ie70dc76d1540cd6a04787cde7cccb4d1bafc7282
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Introduced fdtw_read_string() to read string properties.

Change-Id: I854eef0390632cf2eaddd2dce60cdb98c117de43
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I2f5f64aaf90caae936510e1179392a8835f493e0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

From commit aafd1cf4235d78ce85b76d7da63e9589039344b3:

- lib/libc/strlcpy.c

Change-Id: Iaa7028fcc26706bdd6ee3f1e4bd55dd5873a30c6
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat: juno: fix build for !CSS_USE_SCMI_DRIVER

Several MISRA defect fixes

When CSS_USE_SCMI_DRIVER is not defined or set to 0, we get the
following build error.

plat/arm/board/juno/juno_topology.c:16:19: error: ‘CSS_SCMI_PAYLOAD_BASE’ undeclared here (not in a function)
   .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
                   ^~~~~~~~~~~~~~~~~~~~~
plat/arm/board/juno/juno_topology.c:17:38: error: ‘CSS_SCMI_MHU_DB_REG_OFF’ undeclared here (not in a function)
   .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
                                      ^~~~~~~~~~~~~~~~~~~~~~~
                                      CSS_CPU_PWR_STATE_OFF

Fix the error in order to get function legacy SCPI support functional.

Change-Id: I00cb80db9968aa0be546e33a3a682a2db87719be
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>