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  1. 20 Feb, 2020 1 commit
  3. 07 Feb, 2020 14 commits
  5. 06 Feb, 2020 4 commits
    • Max Shvetsov's avatar
      Adds option to read ROTPK from registers for FVP · a6ffddec
      Max Shvetsov authored 
      

Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
In case of ROT_KEY specified - generates a new hash and replaces the
original.

Note: Juno board was tested by original feature author and was not tested
for this patch since we don't have access to the private key. Juno
implementation was moved to board-specific file without changing
functionality. It is not known whether byte-swapping is still needed
for this platform.

Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
      a6ffddec
    • Louis Mayencourt's avatar
      fvp: Slightly Bump the stack size for bl1 and bl2 · 64271c74
      Louis Mayencourt authored 
      

Stack usage reaches 90% with some configuration. Bump slightly the stack
size to prevent a stack-overflow.

Change-Id: I44ce8b12906586a42f152b7677785fcdc5e78ae1
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      64271c74
    • Carlo Caione's avatar
      amlogic: axg: Add a build flag when using ATOS as BL32 · 72d2535a
      Carlo Caione authored 
      

BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when the
BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to hang
when ATOS (32bit Amlogic BL32 binary-only TEE OS) is used.

Since we are not aware of any Amlogic platform shipping a 64bit version
of ATOS we can hardcode OPTEE_AARCH32 / MODE_RW_32 when using ATOS.
Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
Change-Id: Iaea47cf6dc48bf8a646056761f02fb81b41c78a3
      72d2535a
    • Carlo Caione's avatar
      amlogic: axg: Add support for the A113D (AXG) platform · afd241e7
      Carlo Caione authored 
      

Introduce the preliminary support for the Amlogic A113D (AXG) SoC.

This port is a minimal implementation of BL31 capable of booting
mainline U-Boot, Linux and chainloading BL32 (ATOS).

Tested on a A113D board.
Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
Change-Id: Ic4548fa2f7c48d61b485b2a6517ec36c53c20809
      afd241e7
  7. 05 Feb, 2020 4 commits
  9. 04 Feb, 2020 1 commit
  11. 03 Feb, 2020 1 commit
  13. 31 Jan, 2020 11 commits
    • Pritesh Raithatha's avatar
      Tegra186: memctrl: lock stream id security config · 029b45d1
      Pritesh Raithatha authored 
      

Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      029b45d1
    • Varun Wadekar's avatar
      Tegra194: remove support for simulated system suspend · 8ad1e475
      Varun Wadekar authored 
      

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.

Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8ad1e475
    • Varun Wadekar's avatar
      Tegra194: mce: fix multiple MISRA issues · 4a232d5b
      Varun Wadekar authored 
      

This patch fixes violations of the following MISRA rules

* Rule 8.5  "An external object or function shall be declared once in
             one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
             object with a narrower essential type or of a different
             esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4a232d5b
    • Varun Wadekar's avatar
      Tegra: bpmp: fix multiple MISRA issues · 64aa08fb
      Varun Wadekar authored 
      

This patch fixes violations for the following MISRA rules

* Rule 5.7  "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
             with a narrower essential type or of a different essential type
             category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
             conversions are performed shall have the same essential type
             category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
             shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
             or reserved macro name"

Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      64aa08fb
    • Varun Wadekar's avatar
      Tegra194: se: fix multiple MISRA issues · 8d4107f0
      Varun Wadekar authored 
      

This patch fixes violations for the following MISRA rules

* Rule 8.4  "A compatible declaration shall be visible when an object or
             function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
             conversions are perdormed shall have the same essential type
             category"
* Rule 17.7 "The value returned by a function having non-void return
             type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d4107f0
    • Varun Wadekar's avatar
      Tegra: compile PMC driver for Tegra132/Tegra210 platforms · 57c539f9
      Varun Wadekar authored 
      

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      57c539f9
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler · f561a179
      Varun Wadekar authored 
      

This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f561a179
    • Varun Wadekar's avatar
      Tegra: remove weakly defined per-platform SiP handler · ba37943d
      Varun Wadekar authored 
      

This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.

Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ba37943d
    • Varun Wadekar's avatar
      Tegra: remove weakly defined PSCI platform handlers · e44f86ef
      Varun Wadekar authored 
      

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e44f86ef
    • Varun Wadekar's avatar
      Tegra: remove weakly defined platform setup handlers · 39171cd0
      Varun Wadekar authored 
      

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      39171cd0
    • Varun Wadekar's avatar
      Tegra: per-SoC DRAM base values · 5f1803f9
      Varun Wadekar authored 
      

Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.

Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5f1803f9
  15. 30 Jan, 2020 2 commits
  17. 29 Jan, 2020 2 commits