- 31 Jan, 2019 5 commits
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Varun Wadekar authored
This patch adds a helper function to find the last standing CPU in a cluster. Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds helper functions to help platforms with cluster state entry and exit decisions. * tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate * tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate * tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU? Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt is not direclty wired to the GICD. It goes to the flow controller instead, for power state management. But the flow controller can route the FIQ to the GICD, as a PPI, which can then get routed to the target CPU. This patch adds routines to enable/disable routing the legacy FIQ used by the watchdog timers, to the GICD. Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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steven kao authored
This patch adds support to the bpmp_ipc driver to allow clients to enable/disable clocks to hardware blocks. Currently, the API only supports SE devices. Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90 Signed-off-by: steven kao <skao@nvidia.com>
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Pritesh Raithatha authored
Modifying smmu macros to pass base address of smmu so that it can be used with multiple smmus. Added macro for combining smmu backup regs that can be used for multiple smmus. Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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- 23 Jan, 2019 3 commits
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Varun Wadekar authored
The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform platform specific steps, e.g. enable encryption, save base/size to secure scratch registers. Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP firmware on Tegra SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/ disable requests, module resets among other things. MRQ is short for Message ReQuest. This is the general purpose, multi channel messaging protocol that is widely used to communicate with BPMP. This is further divided into a common high level protocol and a peer-specific low level protocol. The higher level protocol specifies the peer identification, channel definition and allocation, message structure, message semantics and message dispatch process whereas the lower level protocol defines actual message transfer implementation details. Currently, BPMP supports two lower level protocols - Token Mail Operations (TMO), IVC Mail Operations (IMO). This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM Communication) protocol which is a lockless, shared memory messaging queue management protocol. The IVC peer is expected to perform the following as part of establishing a connection with BPMP. 1. Initialize the channels with tegra_ivc_init() or its equivalent. 2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that BPMP is notified via the doorbell. 3. Poll until the channel connection is established [tegra_ivc_channel_notified() return 0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return non zero. The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In future, more hardware blocks would be supported. Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Puneet Saxena authored
Introduce platform handlers to program the MSS settings. This allows the current driver to scale to future chips. Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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- 18 Jan, 2019 6 commits
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Harvey Hsieh authored
This patch cleans the Memory controller's interrupt status register, before exiting to the non-secure world during cold boot. This is required as we observed that the MC's arbitration bit is set before exiting the secure world. Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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Marvin Hsu authored
This change ports the software based SE context save routines. The software implements the context save sequence for SE/SE2 and PKA1. The context save routine is intended to be invoked from the ATF SC7 entry. Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807 Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
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Anthony Zhou authored
MISRA Rule 10.3, the value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The essential type of a enum member is anonymous enum, the enum member should be casted to the right type when using it. Both UL and ULL suffix equal to uint64_t constant in compiler aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix in platform code. So in some case, cast a constant to uint32_t is necessary. Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Steven Kao authored
This patch adds a hook to get the number of smmu devices and removes the NUM_SMMU_DEVICES macro. Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc41 Signed-off-by: Steven Kao <skao@nvidia.com>
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Anthony Zhou authored
Main fixes: Add suffix U for constant [Rule 10.1] Match the operands type [Rule 10.4] Use UL replace U for that constant define that need do "~" operation [Rule 12.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch adds the driver for the general purpose DMA hardware block on newer Tegra SoCs. The GPCDMA is a special purpose DMA used to speed up memory copy operations to/from DRAM and TZSRAM. This patch introduces a macro 'USE_GPC_DMA' to allow platforms to override CPU based memory operations. Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 16 Jan, 2019 3 commits
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Krishna Reddy authored
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO) based on the latest info received from HW team as a part of BW issues debug. SMMU Client config register are obsolete from T186. Clean up the unnecessary register definitions and programming of these registers. Cleanup unnecessary macros as well. Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 1 commit
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Varun Wadekar authored
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 15 Jun, 2017 2 commits
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Anthony Zhou authored
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 13 Apr, 2017 4 commits
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Anthony Zhou authored
Not having U or ULL as a suffix for these enums causes a lot of unnecessary MISRA issues. This patch adds U or ULL suffix to these common enums to reduce number of MISRA issues. Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
During boot, USB3 and flash media (SDMMC/SATA) devices need access to IRAM. Because these clients connect to the MC and do not have a direct path to the IRAM, the MC implements AHB redirection during boot to allow path to IRAM. In this mode, accesses to a programmed memory address aperture are directed to the AHB bus, allowing access to the IRAM. The AHB aperture is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are initialized to disable this aperture. Once bootup is complete, we must program IRAM base/top, thus disabling access to IRAM. This patch provides functionality to disable this access. The tegra port calls this new function before jumping to the non-secure world during cold boot. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 07 Apr, 2017 2 commits
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Pritesh Raithatha authored
This patch empowers the platforms to provide the settings (e.g. stream ID, security setting, transaction overrides) required by the Memory Controller driver. This allows the platforms to program the Memory Controller as per their needs and makes the driver scalable. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch splits the MCE driver into public and private interfaces to allow usage of common functionality across multiple SoCs. Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 05 Apr, 2017 2 commits
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Varun Wadekar authored
This patch moves the TSA block's macros from memctrl_v2.h to tegra_def.h in the Tegra186 tree. Change-Id: I8b45dd3905c5d1f33ffb36d8b2de72aeb06674aa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch moves the chip specific memory controller driver defines to the appropriate tegra_def.h files, for future compatibility. Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 30 Mar, 2017 2 commits
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Varun Wadekar authored
This patch disables TCU prefetch for all the contexts in order to improve SMMU performance. Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables the configuration settings for the TZRAM aperture by programming the base/size of the aperture and restricting access to it. We allow only the CPU to read/write by programming the access configuration registers to 0. Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Mar, 2017 1 commit
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Varun Wadekar authored
This patch fixes the "Recursion in included headers" error flagged by Coverity. Fixes coverity errors "31858: Recursion in included headers" and "31857: Recursion in included headers" Change-Id: Icf8838434b1808b396e743e47f59adc452546364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Mar, 2017 2 commits
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Varun Wadekar authored
This patch adds support to save the BL31 state to the TZDRAM before entering system suspend. The TZRAM loses state during system suspend and so we need to copy the entire BL31 code to TZDRAM before entering the state. In order to restore the state on exiting system suspend, a new CPU reset handler is implemented which gets copied to TZDRAM during boot. TO keep things simple we use this same reset handler for booting secondary CPUs too. Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch reprograms MSS to make ROC deal with ordering of MC traffic after boot and system suspend exit. This is needed as device boots with MSS having all control but POR wants ROC to deal with the ordering. Performance is expected to improve with ROC but since no one has really tested the performance, keep the option configurable for now by introducing a platform level makefile variable. Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 22 Mar, 2017 2 commits
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Varun Wadekar authored
The memory controller loses its settings when the device enters system suspend state. This patch adds a handler to restore the Video Memory settings in the memory controller, which would be called after exiting the system suspend state. Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a device driver for the SMMU hardware block on Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on Tegra186. The driver only supports saving the SMMU settings before entering system suspend. The MC driver and the NS world clients take care of programming their own settings. Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 20 Mar, 2017 1 commit
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Varun Wadekar authored
This patch sets the Memory Controller's TXN_OVERRIDE registers for most write clients to CGID_ADR. This ensures ordering is maintained. In some cases WAW ordering problems could occur. There are different settings for Tegra version A01 v A02. Original changes by Alex Waterman <alexw@nvidia.com> Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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