- 27 Nov, 2018 4 commits
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Chandni Cherukuri authored
For platforms with multi-threaded CPUs, the number of power domains supported would be more than the value currently defined by PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform specific code and let the platform define the number of power domain levels. Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
To support platforms which are based on multi-threaded CPUs, override the weak implementation of plat_arm_get_cpu_pe_count function to return the number of threads supported by the CPU used in the platform. Change-Id: Ia680773f1277b17e2d3d2414d87943dcece33e89 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 26 Nov, 2018 2 commits
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Antonio Niño Díaz authored
Synchronise arch.h and arch_helpers.h with TF-A-Tests
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Antonio Nino Diaz authored
The headers forked at some point in the past and have diverged a lot. In order to make it easier to share code between TF-A-Tests and TF-A, this patch synchronises most of the definitions in the mentioned headers. This is not a complete sync, it has to be followed by more cleanup. This patch also removes the read helpers for the AArch32 instructions ats1cpr and ats1hr (they are write-only). Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 Nov, 2018 2 commits
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Antonio Niño Díaz authored
allwinner: clock / power fixes
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Antonio Niño Díaz authored
Add support for dmc620 tzc driver
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- 22 Nov, 2018 4 commits
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Antonio Nino Diaz authored
This reverts commit 6f512a3d . According to the 'Cortex-A57 MPCore Software Developers Errata Notice': This bug will only affect secure AArch64 EL3. If the above conditions occur, the CPU will not invalidate the targeted EL3 TLB entries and incorrect translations might occur. For this reason it is not needed in AArch32. Change-Id: I6f7b333817515499723e8f306145790ad6af9975 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Niño Díaz authored
xlat v2: Support mapping regions with allocated VA
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Antonio Niño Díaz authored
rcar-gen3: lock RPC hyper-flash access
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Antonio Nino Diaz authored
Provide new APIs to add new regions without specifying the base VA. - `mmap_add_region_alloc_va` adds a static region to mmap choosing as base VA the first possible address after all the currently mapped regions. It is aligned to an appropriate boundary in relation to the size and base PA of the requested region. No attempt is made to fill any unused VA holes. - `mmap_add_dynamic_region_alloc_va` it adds a region the same way as `mmap_add_region_alloc_va` does, but it's dynamic instead of static. - `mmap_add_alloc_va` takes an array of non const `mmap_region_t`, maps them in the same way as `mmap_add_region_alloc_va` and fills their `base_va` field. A helper macro has been created to help create the array, called `MAP_REGION_ALLOC_VA`. Change-Id: I5ef3f82ca0dfd0013d2e8034aa22f13ca528ba37 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Nov, 2018 2 commits
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Vijayenthiran Subramaniam authored
Remove the platform common plat_arm_security_setup function to allow platform specific implementations of the security setup function implemented in the board directory of the platform. For use by secure software, configure region0 of DMC-620 trustzone controller to protect the upper 16MB of memory of the first DRAM block from non-secure accesses. Change-Id: I9a8c19656702c4fa4f6917b3655b692d443bb568 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Vijayenthiran Subramaniam authored
ARM CoreLink DMC-620 Dynamic Memory Controller includes a TZC controller to setup secure or non-secure regions of DRAM memory. The TZC controller allows to setup upto eight such regions of memory in DRAM. This driver provides helper functions to setup the TZC controller within DMC-620. Change-Id: Iee7692417c2080052bdb7b1c2873a024bc5d1d10 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 20 Nov, 2018 5 commits
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Antonio Niño Díaz authored
rpi3: fix bad formatting in rpi3.rst
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Pete Batard authored
d4fd0219 (pull request #1685) introduced unwanted formatting such as bold/italic in the description for RPI3_USE_UEFI_MAP.
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Antonio Niño Díaz authored
backtrace: Extract rules from root Makefile
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Antonio Niño Díaz authored
rpi3: add RPI3_USE_UEFI_MAP build option
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Jorge Ramirez-Ortiz authored
RCAR_RPC_HYPERFLASH_LOCKED can be set to 0 as a build option if the user needs to allow u-boot to reprogram the ATF firmware using a FIP image (as a faster alternative of toggling numerous DIP switches on the board and using ascii-xfer of srec files) The code being controlled with this commit should only be re-enabled for debugging (_never_ on a product release) Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
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- 19 Nov, 2018 4 commits
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Antonio Niño Díaz authored
hikey: increase delay after eMMC initialized
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Antonio Niño Díaz authored
Marvell: Migrate to multi console API
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Antonio Nino Diaz authored
It's better to have them in a separate file instead of having them spread across the Makefile. This is what the stack protector is already doing. Change-Id: Id30742c0af10de5ea6d10674ca25bf52b0f2b262 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Pete Batard authored
The default Raspberry Pi 3 memory mapping for ATF is geared towards the use of uboot + Linux. This creates issues when trying to use ATF with an UEFI payload and Windows on ARM64. We therefore introduce new build option RPI3_USE_UEFI_MAP, that enables the build process to use an alternate memory mapping that is compatible with UEFI + Windows (as well as UEFI + Linux). Fixes ARM-software/tf-issues#649 Signed-off-by: Pete Batard <pete@akeo.ie>
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- 16 Nov, 2018 1 commit
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Antonio Niño Díaz authored
Add multi console support for STM32MP1
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- 15 Nov, 2018 10 commits
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Antonio Niño Díaz authored
rpi3: add RPI3_RUNTIME_UART build option
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Ryan Grachek authored
Some eMMC chips require a longer delay. After testing different chips, 20ms appears to work reliably. Signed-off-by: Ryan Grachek <ryan@edited.us>
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Konstantin Porotchkin authored
Migrate Marvell platforms from legacy console API to multi-console API. Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Yann Gautier authored
Now that MULTI_CONSOLE_API is enabled for the STM32MP1 platform, we can remove the non MULTI_CONSOLE_API parts in the driver. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
When compiling assembly files, stdint.h is not included. UINT32_C and UINT64_C are then not defined. A new GENMASK macro for assembly is then created. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Antonio Niño Díaz authored
SPM priority level changes
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Konstantin Porotchkin authored
According to "openssl" manual: -K key The actual key to use: this must be represented as a string comprised only of hex digits. If only the key is specified, the IV must additionally specified using the -iv option. When both a key and a password are specified, the key given with the -K option will be used and the IV generated from the password will be taken. It does not make much sense to specify both key and password. This patch removes "-k 0" parameter from the encryption command since we are already using "-K" and "-iv" for the key and IV. Change-Id: Ia333cedaa3207e643c95d2ec7c229f50eeab96db Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60745 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Sharon Habet <sharonh@marvell.com>
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- 14 Nov, 2018 6 commits
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Andre Przywara authored
The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is on by default and uses the default voltage. As there seems to be at least on board using a different voltage, add the rail to the list of known voltage lines, so we can setup the right voltage as early as possible. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
The DCDC1 and DCDC5 power rails didn't specify the enable bits. This isn't critical, since those rails are on by default (and are needed for every board), but it is inconsistent. Add the respective enable bits for those two rails. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
The DRIVEVBUS pin setup was broken in two ways: - To configure this pin as an output pin, one has to *clear* the bit in register 0x8f. It is 0 by default, but rebooting from Linux might have left this bit set. - Doing this just configures the pin as an output pin, but doesn't actually drive power to it. This is done via bit 2 in register 0x30. Fix the routine to both properly configure the pin and drive power to it. Add an axp_clrsetbits() helper on the way. Now this isn't really perfect, still: We only need to setup the PMIC power rails that are needed for U-Boot. DRIVEVBUS typically controls the VBUS voltage for the host function of an USB-OTG port, something we typically don't want in U-Boot (fastboot, using the USB *device* functionality, is much more common). The BananaPi-M64 uses the regulator in this way, but the Remix Mini PC actually controls the power of both its USB ports via this line. Technically we should differentiate here: if DRIVEVBUS controls a microUSB-B socket, the power should stay off, any host-type A sockets should be supplied, though. For now just always enable the power, that shouldn't really hurt the USB-OTG functionality anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
The legacy Allwinner ATF port used to setup some clocks, and U-Boot is still relying on this. We don't need to setup the full set, as the SPL is doing most of it, but it misses one clock (AHB2) and programs another (AHB1) to quite conservative values. Fix this up during the platform setup to improve USB and Ethernet performance, iperf values go up by 31% in my setup with that patch. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Sughosh Ganu authored
The current secure partition design mandates that a) at a point, only a single core can be executing in the secure partition, and b) a core cannot be preempted by an interrupt while executing in secure partition. Ensure this by activating the SPM priority prior to entering the parition. Deactivate the priority on return from the partition. Change-Id: Icb3473496d16b733564592eef06304a1028e4f5c Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Register a priority level, PLAT_SP_PRI, for secure partition with EL3 exception handling framework(ehf) module. The secure partition manager(SPM) would raise the core's priority to PLAT_SP_PRI before entering the secure partition, to protect the core from getting interrupted while in secure partition. Change-Id: I686897f052a4371e0efa9b929c07d3ad77249e95 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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