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  1. 26 Jul, 2017 1 commit
    • Sandrine Bailleux's avatar
      xlat lib v2: Expose *_ctx() APIs · a9ad848c
      Sandrine Bailleux authored 
      

In a previous patch, the xlat_ctx_t type has been made public.
This patch now makes the *_ctx() APIs public.

Each API now has a *_ctx() variant. Most of them were already implemented
and this patch just makes them public. However, some of them were missing
so this patch introduces them.

Now that all these APIs are public, there's no good reason for splitting
them accross 2 files (xlat_tables_internal.c and xlat_tables_common.c).
Therefore, this patch moves all code into xlat_tables_internal.c and
removes xlat_tables_common.c. It removes it from the library's makefile
as well.

This last change introduces a compatibility break for platform ports
that specifically include the xlat_tables_common.c file instead of
including the library's Makefile. The UniPhier platform makefile has
been updated to now omit this file from the list of source files.

The prototype of mmap_add_region_ctx() has been slightly changed. The
mmap_region_t passed in argument needs to be constant because it gets
called from map_add(), which receives a constant region. The former
implementation of mmap_add() used to cast the const qualifier away,
which is not a good practice.

Also remove init_xlation_table(), which was a sub-function of
init_xlat_tables(). Now there's just init_xlat_tables() (and
init_xlat_tables_ctx()). Both names were too similar, which was
confusing. Besides, now that all the code is in a single file,
it's no longer needed to have 2 functions for that.

Change-Id: I4ed88c68e44561c3902fbebb89cb197279c5293b
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      a9ad848c
  3. 25 Jul, 2017 4 commits
    • Sandrine Bailleux's avatar
      xlat lib v2: Export translation context as an opaque type · 55c84964
      Sandrine Bailleux authored 
      

At the moment, the translation context type (xlat_ctx_t) is a private
type reserved for the internal usage of the translation table library.
All exported APIs (implemented in xlat_tables_common.c) are wrappers
over the internal implementations that use such a translation context.

These wrappers unconditionally pass the current translation context
representing the memory mappings of the executing BL image. This means
that the caller has no control over which translation context the
library functions act on.

As a first step to make this code more flexible, this patch exports
the 'xlat_ctx_t' type. Note that, although the declaration of this type
is now public, its definition stays private. A macro is introduced to
statically allocate and initialize such a translation context.

The library now internally uses this macro to allocate the default
translation context for the running BL image.

Change-Id: Icece1cde4813fac19452c782b682c758142b1489
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      55c84964
    • Sandrine Bailleux's avatar
      xlat lib: Reorganize architectural defs · 8933c34b
      Sandrine Bailleux authored 
      

Move the header files that provide translation tables architectural
definitions from the library v2 source files to the library include
directory. This allows to share these definitions between both
versions (v1 and v2) of the library.

Create a new header file that includes the AArch32 or AArch64
definitions based on the AARCH32 build flag, so that the library user
doesn't have to worry about handling it on their side.

Also repurpose some of the definitions the header files provide to
concentrate on the things that differ between AArch32 and AArch64.
As a result they now contain the following information:
 - the first table level that allows block descriptors;
 - the architectural limits of the virtual address space;
 - the initial lookup level to cover the entire address space.

Additionally, move the XLAT_TABLE_LEVEL_MIN macro from
xlat_tables_defs.h to the AArch32/AArch64 architectural definitions.

This new organisation eliminates duplicated information in the AArch32
and AArch64 versions. It also decouples these architectural files from
any platform-specific information. Previously, they were dependent on
the address space size, which is platform-specific.

Finally, for the v2 of the library, move the compatibility code for
ADDR_SPACE_SIZE into a C file as it is not needed outside of this
file. For v1, this code hasn't been changed and stays in a header
file because it's needed by several files.

Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      8933c34b
    • Sandrine Bailleux's avatar
      FVP: Do not map DEVICE2 memory range when TBB is disabled · 284c3d67
      Sandrine Bailleux authored 
      

The DEVICE2 memory range is needed to access the Root of Trust Public
Key registers. This is not needed when Trusted Board Boot is disabled
so it's safer to not map it in this case. This also saves one level-2
page table in each of BL1 and BL2 images.

Also add some comments.

Change-Id: I67456b44f3fd5e145f6510a8499b7fdf720a7273
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      284c3d67
    • Sandrine Bailleux's avatar
      xlat lib v2: Print some debug statistics · 0350bc6d
      Sandrine Bailleux authored 
      

This patch adds some debug prints to display some statistics about page
tables usage. They are printed only if the LOG_LEVEL is at least 50
(i.e. VERBOSE).

Sample output for BL1:

VERBOSE:    Translation tables state:
VERBOSE:      Max allowed PA:  0xffffffff
VERBOSE:      Max allowed VA:  0xffffffff
VERBOSE:      Max mapped PA:   0x7fffffff
VERBOSE:      Max mapped VA:   0x7fffffff
VERBOSE:      Initial lookup level: 1
VERBOSE:      Entries @initial lookup level: 4
VERBOSE:      Used 4 sub-tables out of 5 (spare: 1)

Change-Id: If38956902e9616cdcd6065ecd140fe21482597ea
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      0350bc6d
  5. 20 Jul, 2017 1 commit
  7. 14 Jul, 2017 6 commits
    • davidcunado-arm's avatar
      Merge pull request #1005 from ldts/v1 · 4deb7bcc
      davidcunado-arm authored 
      Poplar: Initial commit for Poplar E-96Boards
      4deb7bcc
    • davidcunado-arm's avatar
      Merge pull request #1028 from vchong/bl32_optee_support_v2 · 8f83003b
      davidcunado-arm authored 
      hikey: Add BL32 (OP-TEE) support v2
      8f83003b
    • Jorge Ramirez-Ortiz's avatar
      Poplar: Initial commit for Poplar E-96Boards · e35d0edb
      Jorge Ramirez-Ortiz authored 
      The board features the Hi3798C V200 with an integrated quad-core
64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
making it capable of running any commercial set-top solution based on
Linux or Android. Its high performance specification also supports a
premium user experience with up to H.265 HEVC decoding of 4K video at
60 frames per second.

SOC  Hisilicon Hi3798CV200
CPU  Quad-core ARM Cortex-A53 64 bit
DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
USB  Two USB 2.0 ports One USB 3.0 ports
CONSOLE  USB-micro port for console support
ETHERNET  1 GBe Ethernet
PCIE  One PCIe 2.0 interfaces
JTAG  8-Pin JTAG
EXPANSION INTERFACE  Linaro 96Boards Low Speed Expansion slot
DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
WIFI  802.11AC 2*2 with Bluetooth
CONNECTORS  One connector for Smart Card One connector for TSI

The platform boot sequence is as follows:
    l-loader --> arm_trusted_firmware --> u-boot

Rep...
      e35d0edb
    • davidcunado-arm's avatar
      Merge pull request #1027 from vchong/960_bl32_optee_support · 37debcc6
      davidcunado-arm authored 
      hikey960 updates
      37debcc6
    • Isla Mitchell's avatar
      Fix order of remaining platform #includes · ee1ebbd1
      Isla Mitchell authored 
      

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.

Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: default avatarIsla Mitchell <isla.mitchell@arm.com>
      ee1ebbd1
    • Isla Mitchell's avatar
      Fix order of ARM platform #includes · 4adb10c1
      Isla Mitchell authored 
      

This fix modifies the order of #includes in ARM standard platforms
to meet the ARM TF coding standard.

Change-Id: Ide19aad6233babda4eea2d17d49e523645fed1b2
Signed-off-by: default avatarIsla Mitchell <isla.mitchell@arm.com>
      4adb10c1
  9. 12 Jul, 2017 8 commits
  11. 11 Jul, 2017 1 commit
  13. 10 Jul, 2017 4 commits
  15. 07 Jul, 2017 3 commits
  17. 06 Jul, 2017 7 commits
  19. 05 Jul, 2017 4 commits
  21. 02 Jul, 2017 1 commit