- 06 Feb, 2020 1 commit
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Carlo Caione authored
Introduce the preliminary support for the Amlogic A113D (AXG) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot, Linux and chainloading BL32 (ATOS). Tested on a A113D board. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic4548fa2f7c48d61b485b2a6517ec36c53c20809
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- 26 Sep, 2019 1 commit
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Carlo Caione authored
Introduce the preliminary support for the Amlogic S905X2 (G12A) SoC. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux. Tested on a SEI510 board. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ife958f10e815a4530292c45446adb71239f3367f
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- 18 Sep, 2019 1 commit
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Carlo Caione authored
The registers location for the SHA DMA driver is not unique for the different platforms. Move the mapping out of the driver and into the platform-specific header. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129
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- 17 Sep, 2019 1 commit
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Carlo Caione authored
Both kernel and U-Boot use a SMC call to the secure monitor to get the chip ID. This call is translated by BL31 to a call to the SCP to retrieve the ID. Add a new SiP call and the backing SCPI command. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ib128f5645ee92866e7ebbcd550dacd33f573524b
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- 11 Sep, 2019 1 commit
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Carlo Caione authored
Make the header guards more generic and contextually remove the GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I842fa2e084e71280ae17b39c67877e844821a171
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- 05 Sep, 2019 7 commits
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Carlo Caione authored
Remove the GXBB prefix where needed and add SoC specific prefixes for GXBB/GXL. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27
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Carlo Caione authored
Remove the GXBB prefix from the code in the common directory and add SoC-specific prefixes in the SoC specific code. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030
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Carlo Caione authored
Make the MHU code AML specific adding a new aml_* prefix and remove the GXBB prefix from the register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2
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Carlo Caione authored
All the SIP/SVC related code is currently the same between GXL and GXBB. Rename function names and register names to avoid hardcoding the GXBB prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf
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Carlo Caione authored
Fixing at the same time the related register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ib1130d50abe6088f1c0826878d1ae454a0f23008
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Carlo Caione authored
The code is the common directory is now generic, no need to have the SoC prefix hardcoded in the function names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1
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Carlo Caione authored
Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
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- 02 Aug, 2019 1 commit
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Remi Pommarel authored
Before CPU enters standby state (wfi), the AP needs to signal the SCP through PSCI mailbox. Also at boot time the AP has to wait for the SCP to be ready before sending the first scpi commands or it can crash. Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6 Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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- 02 Apr, 2019 1 commit
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Antonio Nino Diaz authored
The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested on a lepotato. Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 26 Oct, 2018 1 commit
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Antonio Nino Diaz authored
The Amlogic Meson S905 is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested in an ODROID-C2. Change-Id: Ia4bc82d7aca42a69d6b118b947279f82b3f6c6da Tested-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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