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Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded while
rebasing.

Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d
Fixes: 627298d4

 ("dts: stm32mp157c: add etzpc node")
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

64KB was not enouth to handle fdt, bl2 shows
following error message.

"ERROR:   Invalid Device Tree at 0x10000000000: error -3"

This patch increases the size to 1MB to address above error.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I0726a0cea95087175451da0dba7410acd27df808

* changes:
  plat/stm32mp1: sp_min relies on etzpc driver
  dts: stm32mp157c: add etzpc node
  drivers: introduce ST ETZPC driver

* changes:
  Enable ARMv8.6-ECV Self-Synch when booting to EL2
  Enable ARMv8.6-FGT when booting to EL2

Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign both to secure world only.

Define stm32mp15 SoC identifiers for the platform specific DECPROT
instances.

Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Add a node for the ETZPC device so that driver initializes during
stm32mp15* boot sequence.

Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

ETZPC stands for Extended TrustZone Protection Controller. It is a
resource conditional access device. It is mainly based on Arm TZPC.

ST ETZPC exposes memory mapped DECPROT cells to set access permissions
to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some
of the SoC internal memories.

ST ETZPC exposes memory mapped TZMA cells to set access permissions
to some SoC internal memories.

Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570
Co-developed-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

This patch enables the stream ID for the SD/MMC
controllers via dedicated unit register. Thanks to this
change it is possible to configure properly the
IOMMU in OS and use the SD/MMC interface in a guest
Virtual Machine.

Change-Id: I99cbd2c9882eb558ba01405d3d8a3e969f06e082
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>

BL31_CACHE_DISABLE flag was introduced as a work-around
for the older SoC revisions. Since it is not relevant in the
newest versions, toggle it to be disabled by default.
One can still specify it by adding 'BL31_CACHE_DISABLE=1'
string to the build command.

Change-Id: I11b52dade3ff7f8ee643b8078c6e447c45946570
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Enhanced Counter Virtualization, ECV, is an architecture extension introduced
in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the
control register to enable this extension when booting a hypervisor at EL2.

Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

The Fine Grained Traps (FGT) architecture extension was added to aarch64 in
ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific
instructions in a more fine grained manner, with an enable bit for each
instruction. This patch adds support for this extension by enabling the
extension when booting an hypervisor at EL2.

Change-Id: Idb9013ed118b6a1b7b76287237096de992ca4da3
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

This should allow git to easily track file moves
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

The patch fixes BL31 linker script error
"Init code ends past the end of the stacks"
for platforms with number of CPUs less than 4,
which is caused by __STACKS_END__ address being
lower than __INIT_CODE_END__.
The modified BL31 linker script detects such cases
and increases the total amount of stack memory,
setting __STACKS_END__ = __INIT_CODE_END__, and
CPUs' stacks are calculated by BL31 'plat_get_my_stack'
function accordingly. For platforms with more than 4 CPUs
and __INIT_CODE_END__ < __STACKS_END__ stack memory does not
increase and allocated CPUs' stacks match the existing
implementation.
The patch removes exclusion of PSCI initialization
functions from the reclaimed .init section in
'arm_reclaim_init.ld.S' script, which increases the
size of reclaimed memory region.

Change-Id: I927773e00dd84e1ffe72f9ee534f4f2fc7b6153c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

As per the trustedfirmware.org Project Maintenance Process [1], the
current maintainers of the TF-A project have nominated some contributors
to become maintainers themselves. List them in the maintainers.rst file
to make this official.

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/



Change-Id: Id4e3cfd12a9074f4e255087fa5dd6fa5f902845f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Extend the list of modules and assign code owners to each of them.

Change-Id: I267b87d8e239c7eff143b4c7e6ce9712fcf7101e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>