GitLab

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Introduce platform handlers to reprogram the MSS settings.

Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Need to use bitwise & instead of condition &&.

Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.

Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch adds platform support for the Memory Controller and
SMMU drivers, for the Tegra194 SoC.

Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

GPU, MPCORE and PTC clients are changed and not going through SMMU.
Removing it from streamid list.

Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

This patch adds support for all three SMMU devices present on the SoC.

The following changes have been done:
    Add SMMU devices to the memory map
    Update register read and write functions

Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.

Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>