1. 01 Jun, 2021 1 commit
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix configuring UART clock · b9185c75
      Pali Rohár authored
      
      
      When configuring the UART_BAUD_REG register, the function
      console_a3700_core_init() currently only changes the baud divisor field,
      leaving other fields to their previous value.
      
      This is incorrect, because the baud divisor is computed with the
      assumption that the parent clock rate is 25 MHz, and since the other
      fields in this register configure the parent clock, which could have
      been changed by U-Boot or Linux.
      
      Fix this function to also configure the other fields so that the UART
      parent clock is selected to be the xtal clock.
      
      For example without this change TF-A prints only
      
          ERROR: a3700_system_off needs to be implemented
      
      followed by garbage after plat_crash_console_init() is called.
      
      After applying this change instead of garbage it also print crash info:
      
          PANIC at PC : 0x0000000004023800
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
      b9185c75
  2. 28 May, 2021 1 commit
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation · 66a77528
      Pali Rohár authored
      
      
      UART parent clock is by default the platform's xtal clock, which is
      25 MHz.
      
      The value defined in the driver, though, is 25.8048 MHz. This is a hack
      for the suboptimal divisor calculation
        Divisor = UART clock / (16 * baudrate)
      which does not use rounding division, resulting in a suboptimal value
      for divisor if the correct parent clock rate was used.
      
      Change the code for divisor calculation to
        Divisor = Round(UART clock / (16 * baudrate))
      and change the parent clock rate value to 25 MHz.
      
      The final UART divisor for default baudrate 115200 is not affected by
      this change.
      
      (Note that the parent clock rate should not be defined via a macro,
      since the xtal clock can also be 40 MHz. This is outside of the scope of
      this fix, though.)
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
      66a77528
  3. 17 May, 2021 3 commits
  4. 14 May, 2021 3 commits
  5. 13 May, 2021 3 commits
  6. 12 May, 2021 3 commits
  7. 07 May, 2021 2 commits
  8. 05 May, 2021 3 commits
  9. 04 May, 2021 2 commits
  10. 30 Apr, 2021 14 commits
  11. 29 Apr, 2021 5 commits