- 19 Jul, 2016 2 commits
-
-
Soby Mathew authored
This patch moves the `arm_common.c` file from `plat/arm/common/aarch64/` to the parent directory since the functions implemented in the file are not AArch64 specific. The platform makefiles are also modified for this change. Change-Id: I776d2e4958f59041476cf2f53a9adb5b2d304ee0
-
Soby Mathew authored
The `plat_psci_common.c` was moved to the new location `plat/common` and a stub file was retained at previous location for compatibility. This patch modifies the platform makefiles to include the file from the new location. Change-Id: Iabddeeb824e9a5d72d176d7c644735966c8c0699
-
- 18 Jul, 2016 2 commits
-
-
Soby Mathew authored
This patch moves the PSCI services and BL31 frameworks like context management and per-cpu data into new library components `PSCI` and `el3_runtime` respectively. This enables PSCI to be built independently from BL31. A new `psci_lib.mk` makefile is introduced which adds the relevant PSCI library sources and gets included by `bl31.mk`. Other changes which are done as part of this patch are: * The runtime services framework is now moved to the `common/` folder to enable reuse. * The `asm_macros.S` and `assert_macros.S` helpers are moved to architecture specific folder. * The `plat_psci_common.c` is moved from the `plat/common/aarch64/` folder to `plat/common` folder. The original file location now has a stub which just includes the file from new location to maintain platform compatibility. Most of the changes wouldn't affect platform builds as they just involve changes to the generic bl1.mk and bl31.mk makefiles. NOTE: THE `plat_psci_common.c` FILE HAS MOVED LOCATION AND THE STUB FILE AT THE ORIGINAL LOCATION IS NOW DEPRECATED. PLATFORMS SHOULD MODIFY THEIR MAKEFILES TO INCLUDE THE FILE FROM THE NEW LOCATION. Change-Id: I6bd87d5b59424995c6a65ef8076d4fda91ad5e86
-
Soby Mathew authored
This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as listed below: * Use uintptr_t for storing address instead of uint64_t or unsigned long. * Review usage of unsigned long as it can no longer be assumed to be 64 bit. * Use u_register_t for register values whose width varies depending on whether AArch64 or AArch32. * Use generic C types where-ever possible. In addition to the above changes, this patch also modifies format specifiers in print invocations so that they are AArch64/AArch32 agnostic. Only files related to upcoming feature development have been reworked. Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
-
- 08 Jul, 2016 8 commits
-
-
Sandrine Bailleux authored
On ARM CSS platforms, the whole flash used to be mapped as executable. This is not required, given that the flash is used to store the BL1 and FIP images and: - The FIP is not executed in place, its images are copied to RAM and executed from there. - BL1 is executed in place from flash but only its code needs to be mapped as executable and platform code takes care of re-mapping BL1's read-only section as executable. Therefore, this patch now maps the flash as non-executable by default on these platforms. This increases security by restricting the executable region to what is strictly needed. This patch also adds some comments to clarify the memory mapping attributes on these platforms. Change-Id: I4db3c145508bea1f43fbe0f6dcd551e1aec1ecd3
-
Sandrine Bailleux authored
This patch adds some verbose traces in the arm_setup_page_tables() function to print the extents of the different memory regions it maps. Change-Id: Ia3ae1053e7ebf3579601ff9238b0e3791eb1e9e4
-
Sandrine Bailleux authored
The arm_setup_page_tables() function used to expect a single set of addresses defining the extents of the whole read-only section, code and read-only data mixed up, which was mapped as executable. This patch changes this behaviour. arm_setup_page_tables() now expects 2 separate sets of addresses: - the extents of the code section; - the extents of the read-only data section. The code is mapped as executable, whereas the data is mapped as execute-never. New #defines have been introduced to identify the extents of the code and the read-only data section. Given that all BL images except BL1 share the same memory layout and linker script structure, these #defines are common across these images. The slight memory layout differences in BL1 have been handled by providing values specific to BL1. Note that this patch also affects the Xilinx platform port, which uses the arm_setup_page_tables() function. It has been updated accordingly, such that the memory mappings on this platform are unchanged. This is achieved by passing null values as the extents of the read-only data section so that it is ignored. As a result, the whole read-only section is still mapped as executable. Fixes ARM-software/tf-issues#85 Change-Id: I1f95865c53ce6e253a01286ff56e0aa1161abac5
-
Sandrine Bailleux authored
This patch changes the base address of the "total" Trusted SRAM region seen by the BL2U image. It used to start just after BL2U's read-only section (i.e. at address BL2U_RO_LIMIT), it now starts from the base address of the BL2U image (i.e. at address BL2U_BASE). In other words, the "total" memory region now includes BL2U's own read-only section. This does not change BL2U's resulting memory mappings because the read-only section was already mapped in BL2U, it just wasn't part of this total memory region. Change-Id: I2da16ac842469023b41904eaa8d13ed678d65671
-
Sandrine Bailleux authored
At the moment, on ARM platforms, BL1 maps everything from BL1_RO_BASE to BL1_RO_LIMIT. BL1_RO_LIMIT, as defined in the porting guide, is the maximum address in Trusted ROM that BL1's actual content _can_ occupy. The actual portion of ROM occupied by BL1 can be less than that, which means that BL1 might map more Trusted ROM than it actually needs to. This patch changes BL1's memory mappings on ARM platforms to restrict the region of Trusted ROM it maps. It uses the symbols exported by the linker to figure out the actual extents of BL1's ROM footprint. This change increases the number of page tables used on FVP by 1. On FVP, we used to map the whole Trusted ROM. As it is 64MB large, we used to map it as blocks of 2MB using level-2 translation table entries. We now need a finer-grained mapping, which requires an additional level-3 translation table. On ARM CSS platforms, the number of translation tables is unchanged. The BL1 image resides in flash at address 0x0BEC0000. This address is not aligned on a 2MB-boundary so a level-3 translation table was already required to map this memory. Change-Id: I317a93fd99c40e70d0f13cc3d7a570f05c6c61eb
-
Sandrine Bailleux authored
This patch introduces a new header file: include/lib/utils.h. Its purpose is to provide generic macros and helper functions that are independent of any BL image, architecture, platform and even not specific to Trusted Firmware. For now, it contains only 2 macros: ARRAY_SIZE() and IS_POWER_OF_TWO(). These were previously defined in bl_common.h and xlat_tables.c respectively. bl_common.h includes utils.h to retain compatibility for platforms that relied on bl_common.h for the ARRAY_SIZE() macro. Upstream platform ports that use this macro have been updated to include utils.h. Change-Id: I960450f54134f25d1710bfbdc4184f12c049a9a9
-
Sandrine Bailleux authored
This patch introduces the arm_setup_page_tables() function to set up page tables on ARM platforms. It replaces the arm_configure_mmu_elx() functions and does the same thing except that it doesn't enable the MMU at the end. The idea is to reduce the amount of per-EL code that is generated by the C preprocessor by splitting the memory regions definitions and page tables creation (which is generic) from the MMU enablement (which is the only per-EL configuration). As a consequence, the call to the enable_mmu_elx() function has been moved up into the plat_arch_setup() hook. Any other ARM standard platforms that use the functions `arm_configure_mmu_elx()` must be updated. Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d
-
Soby Mathew authored
The per-cpu stacks should be aligned to the cache-line size and the `declare_stack` helper in asm_macros.S macro assumed a cache-line size of 64 bytes. The platform defines the cache-line size via CACHE_WRITEBACK_GRANULE macro. This patch modifies `declare_stack` helper macro to derive stack alignment from the platform defined macro. Change-Id: I1e1b00fc8806ecc88190ed169f4c8d3dd25fe95b
-
- 16 Jun, 2016 1 commit
-
-
Soby Mathew authored
This patch enables optional PSCI functions `PSCI_STAT_COUNT` and `PSCI_STAT_RESIDENCY` for ARM standard platforms. The optional platform API 'translate_power_state_by_mpidr()' is implemented for the Juno platform. 'validate_power_state()' on Juno downgrades PSCI CPU_SUSPEND requests for the system power level to the cluster power level. Hence, it is not suitable for validating the 'power_state' parameter passed in a PSCI_STAT_COUNT/RESIDENCY call. Change-Id: I9548322676fa468d22912392f2325c2a9f96e4d2
-
- 15 Jun, 2016 1 commit
-
-
Soren Brinkmann authored
Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd UART available in the SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
-
- 09 Jun, 2016 1 commit
-
-
Jens Wiklander authored
This patch adds support for the QEMU virt ARMv8-A target. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
-
- 08 Jun, 2016 1 commit
-
-
David Wang authored
In GICv3 mode, the non secure group1 interrupts are signalled via the FIQ line in EL3. To support waking up from CPU_SUSPEND to standby on these systems, EL3 should route FIQ to EL3 temporarily before wfi and restore the original setting after resume. This patch makes this change for the CSS platforms in the `css_cpu_standby` psci pm ops hook. Change-Id: Ibf3295d16e2f08da490847c1457bc839e1bac144
-
- 07 Jun, 2016 1 commit
-
-
Mirela Simonovic authored
NODE_IPI_APU is the node ID of APU's IPI device. If APU should be woken-up on an IPI from FPD power down, this node shall be set as the wake-up source upon suspend. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
-
- 03 Jun, 2016 2 commits
-
-
Sandrine Bailleux authored
Building TF with ERROR_DEPRECATED=1 fails because of a missing semi-column. This patch fixes this syntax error. Change-Id: I98515840ce74245b0a0215805f85c8e399094f68
-
Antonio Nino Diaz authored
Replaced placeholder implementation of plat_set_nv_ctr for FVP platforms by a working one. On FVP, the mapping of region DEVICE2 has been changed from RO to RW to prevent exceptions when writing to the NV counter, which is contained in this region. Change-Id: I56a49631432ce13905572378cbdf106f69c82f57
-
- 01 Jun, 2016 1 commit
-
-
Yatharth Kochar authored
This patch adds ARM Cortex-A73 MPCore Processor support in the CPU specific operations framework. It also includes this support for the Base FVP port. Change-Id: I0e26b594f2ec1d28eb815db9810c682e3885716d
-
- 29 May, 2016 2 commits
-
-
Soren Brinkmann authored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Soren Brinkmann authored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
- 27 May, 2016 4 commits
-
-
Caesar Wang authored
if define power off gpio, BL31 will do system power off through gpio control.
-
Caesar Wang authored
If define a reset gpio, BL31 will use gpio to reset SOC, otherwise use CRU reset.
-
Caesar Wang authored
We add plat parameter structs to support BL2 to pass variable-length, variable-type parameters to BL31. The parameters are structured as a link list. During bl31 setup time, we travse the list to process each parameter. throuth this way, we can get the reset or power off gpio parameter, and do hardware control in BL31. This structure also can pass other parameter to BL31 in future.
-
Caesar Wang authored
There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs on rk3399 platform. The pull direction(pullup or pulldown) for all of GPIOs are software-programmable. At the moment, we add the gpio basic driver since reset or power off the devices from gpio configuration for BL31.
-
- 25 May, 2016 3 commits
-
-
Soren Brinkmann authored
Powering up cores didn't wait for the PMUFW to complete the request, which could result in cores failing to power up in Linux. Reported-by: Koteswararao Nayudu <kotin@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Soby Mathew authored
This patch adds support to select CCN driver for FVP during build. A new build option `FVP_INTERCONNECT_DRIVER` is added to allow selection between the CCI and CCN driver. Currently only the CCN-502 variant is supported on FVP. The common ARM CCN platform helper file now verifies the cluster count declared by platform is equal to the number of root node masters exported by the ARM Standard platform. Change-Id: I71d7b4785f8925ed499c153b2e9b9925fcefd57a
-
Soren Brinkmann authored
The revision field may change between silicon revisions without changing the mapping to a part. This avoids errors like: ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093 NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000 on parts with a newer revision. Reported-by: Love Kumar <love.kumar@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Love Kumar <love.kumar@xilinx.com>
-
- 24 May, 2016 6 commits
-
-
Stefan Krsmanovic authored
Access to APU_PWRCTRL register is protected during suspend/wakeup pocedure in order to save valid state. If more than one CPU is accessing this register it can be left in corrupted state during read-modify-write process. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Stefan Krsmanovic authored
DEFINE_BAKERY_LOCK() macro is used to put lock in coherent memory region. ARM Trusted Firmware design guide, chapter 11 states that bakery_lock data structures should be allocated in coherent memory region because it is accessed by multiple CPUs with mismatched shareability, cacheability and memory attributes. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Anes Hadziahmetagic authored
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Anes Hadziahmetagic authored
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Filip Drazic authored
Functions pm_ipi_send and pm_ipi_send_sync are declared in pm_ipi.h Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
-
Soren Brinkmann authored
The GIC area is specified larger than it needs to be and can be reduced. Which allows reducing the structures required for the translation tables as well. This results in a reduction of memory footprint of ca. 4k. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
-
- 20 May, 2016 5 commits
-
-
Antonio Nino Diaz authored
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
-
Antonio Nino Diaz authored
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e
-
Antonio Nino Diaz authored
Added a build flag to select the generic delay timer on FVP instead of the SP804 timer. By default, the generic one will be selected. The user guide has been updated. Change-Id: Ica34425c6d4ed95a187b529c612f6d3b26b78bc6
-
Antonio Nino Diaz authored
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all upstream platforms. Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
-
Antonio Nino Diaz authored
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit plat_get_syscnt_freq. The old one has been flagged as deprecated. Common code has been updated to use this new version. Porting guide has been updated. Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e
-