- 17 Jun, 2019 37 commits
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Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by:Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I46b445a77b39412e7a41ae0e0e087a409d0c22e3
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Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: -
Marek Vasut authored
The DBSC QoS settings can be programmed by iterating over a table with register-value pairs and writing those to the registers, add function to do just that. Subsequent patches will convert the DBSC QoS setting functions for each SoC to this new function. Signed-off-by: -
Marek Vasut authored
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
Convert the mstat table from a complex structure to simple sequence of uint64_t values, since the structure described just that and the loop can operate over incrementing sequence of addresses just fine. Signed-off-by: -
Marek Vasut authored
Pull out the mstat fix array into separate file, to align the structure of the driver with the other SoCs. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the V3M QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by: -
Marek Vasut authored
The extra level of nesting is not necessary, drop it. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the E3 QoS init. No functional change. Signed-off-by: -
Marek Vasut authored
Replace the remaining ad-hoc register addresses with proper macros. Signed-off-by: -
Marek Vasut authored
The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: -
Marek Vasut authored
Move the DBSC write enabling and disabling to dbsc_setting() function, to make it local, instead of having it all over the code. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
Convert the mstat table from a complex structure to simple sequence of uint64_t values, since the structure described just that and the loop can operate over incrementing sequence of addresses just fine. Signed-off-by: -
Marek Vasut authored
Pull out the mstat fix array into separate file, to align the structure of the driver with the other SoCs. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the D3 QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by: -
Marek Vasut authored
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: -
Marek Vasut authored
The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
The extra level of nesting is not necessary, drop it. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the M3N QoS init. No functional change. Signed-off-by: -
Marek Vasut authored
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: -
Marek Vasut authored
The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
The extra level of nesting is not necessary, drop it. No functional change. Signed-off-by: -
Marek Vasut authored
Convert the mstat table from a complex structure to simple sequence of uint64_t values, since the structure described just that and the loop can operate over incrementing sequence of addresses just fine. Signed-off-by: -
Marek Vasut authored
Pull out the mstat fix array into separate file, to align the structure of the driver with the other SoCs. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the M3W QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by: -
Marek Vasut authored
Fix checkpatch issues, clean up macro indentation. No functional change. Signed-off-by: -
Marek Vasut authored
The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: -
Marek Vasut authored
Drop useless comments in dbsc_setting(). No functional change. Signed-off-by: -
Marek Vasut authored
The extra level of nesting is not necessary, drop it. No functional change. Signed-off-by: -
Marek Vasut authored
Convert the mstat table from a complex structure to simple sequence of uint64_t values, since the structure described just that and the loop can operate over incrementing sequence of addresses just fine. Signed-off-by: -
Marek Vasut authored
Pull out the mstat fix array into separate file, to align the structure of the driver with the other SoCs. No functional change. Signed-off-by: -
Marek Vasut authored
Use common qos_regs.h instead of a local copy in the H3 QoS init. Fill missing registers into qos_regs.h . No functional change. Signed-off-by:
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- 13 Jun, 2019 1 commit
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Marek Vasut authored
Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by:
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- 05 Jun, 2019 1 commit
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James kung authored
According to Arm GIC spec(IHI0069E, section 4.6.1), when GICD_CTLR.DS == 0, Secure Group 1 interrupts are treated as Group 0 by a CPU interface if: - The PE does not implement EL3. - ICC_SRE_EL1(S).SRE == 0 When a cpu enter suspend or deep idle, it might be powered off. When the cpu resume, according to the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and 9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if write is allowed) and G0/G1S/G1NS interrupt of the GIC cpu interface are all disabled. If a G1S SPI interrupt occurred and the target cpu of the SPI is assigned to a specific cpu which is in suspend and is powered off, when the cpu resume and start to initial the GIC cpu interface, the initial sequence might affect the interrupt group type of the pending interrupt on the cpu interface. Current initial sequence on the cpu interface is: 1. Enable G0 interrupt 2. Enable G1S interrupt 3. Enable ICC_SRE_EL1(S).SRE It is possible to treat the pending G1S interrupt as G0 interrupt on the cpu interface if the G1S SPI interrupt occurred between step2 and step3. To prevent the above situation happend, the initial sequence should be changed as follows: 1. Enable ICC_SRE_EL1(S).SRE 2. Enable G0 interrupt 3. Enable G1S interrupt Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0 Signed-off-by:James Kung <kong1191@gmail.com>
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- 23 May, 2019 1 commit
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Masahisa Kojima authored
Payload length of the get dram mapping information message is 0. The mbx_mem->len parameter should be 4, it only contains message header. Fixes: b67d2029 ("plat/synquacer: enable SCMI support") Signed-off-by:
Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: If1cd4c855da2dc5dc4b6da3bea152b8441971de7
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