Skip to content

GitLab

Switch branch/tag
  1. 03 Apr, 2020 5 commits
  3. 31 Mar, 2020 1 commit
  5. 30 Mar, 2020 3 commits
  7. 27 Mar, 2020 2 commits
    • Aditya Angadi's avatar
      plat/arm/sgi: fix the incorrect check for SCMI channel ID · 5c215de2
      Aditya Angadi authored 
      

Use ARRAY_SIZE macro instead of sizeof operator to obtain the maximum
number of SCMI channels supported on the platform.

Change-Id: Id922bb548af98ac99b4ac0c34e38e589e5a80b2d
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      5c215de2
    • Zelalem's avatar
      Flush dcache when storing timestamp · f27b6924
      Zelalem authored 
      

On DynamIQ CPU FVPs, stats test cases are failing when
hardware-assisted coherency is enabled due to a corrupt
timestamp value. Investigation of the issue indicates that
on these models the timestamp value is stored in cache
instead of memory. This patch flushes the dcache when the
timestamp is stored to make sure it is stored in memory.

Change-Id: I05cd54ba5991a5a96dd07f1e08b5212273201411
Signed-off-by: default avatarZelalem <zelalem.aweke@arm.com>
      f27b6924
  9. 26 Mar, 2020 12 commits
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Compile with additional CPU libraries · 4b5793c9
      Oliver Swede authored 
      

This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.

BL31 behaves differently depending on whether or not the CPUs in the
system use cache coherency, and as a result any CPU libraries that are
compiled together must serve processors that are consistent in this
regard.

This compiles a different set of CPU libraries depending on whether or
not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the
CPUs support hardware-level support for cache coherency. This build
flag is used in the makefile in the same way as the Arm FVP port.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
      4b5793c9
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Enable position-independent execution · 62056e4e
      Oliver Swede authored 
      

This allows the BL31 port to run with position-independent execution
enabled so that it can be ran from any address in the system.
This increases the flexibility of the image, allowing it to be ran from
other locations rather than only its hardcoded absolute address
(currently set to the typical DRAM base of 2GB). This may be useful for
future images that describe system configurations with other memory
layouts (e.g. where SRAM is included).

It does this by setting ENABLE_PIE=1 and changing the absolute
address to 0. The load address of bl31.bin can then be specified by
the -l [load address] argument in the fpga-run command (additionally,
this address is required by any preceding payloads that specify the
start address. For ELF payloads this is usually extracted automatically
by reading the entrypoint address in the header, however bl31.bin is a
different file format so has this additional dependency).
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
      62056e4e
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Enable port for alternative cluster configurations · e726c758
      Oliver Swede authored 
      

This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.

The BL31 port that is uploaded as a payload to the FPGA with an image
should cater for a wide variety of system configurations. This patch
makes the necessary changes to enable it to function with images whose
cluster configurations may be larger (either by utilizing more
clusters, more CPUs per cluster, more threads in each CPU, or a
combination) than the initial image being used for testing.

As part of this, the hard-coded values that configure the size of the
array describing the topology of the power domain tree are increased
to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core.
This ensures the port works with cluster configurations up to these
sizes. When there are too many entries for the number of available PEs,
e.g. if there is a variable number of CPUs between clusters, then there
will be empty entries in the array. This is permitted and the PSCI
library will still function as expected. While this increases its size,
this shouldn't be an issue in the context of the size of BL31, and is
worth the trade-off for the extra compatibility.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
      e726c758
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller · 87762bce
      Oliver Swede authored 
      

This initializes the GIC using the Arm GIC drivers in TF-A.
The initial FPGA image uses a GIC600 implementation, and so that its
power controller is enabled, this platform port calls the corresponding
implementation-specific routines.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
      87762bce
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Initialize the System Counter · 2d696d18
      Oliver Swede authored 
      

This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
      2d696d18
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images · 7ee4db6e
      Oliver Swede authored 
      

This adds a basic PSCI implementation allow secondary CPUs to be
released from an initial state and continue through to the warm boot
entrypoint.

Each secondary CPU is kept in a holding pen, whereby it polls the value
representing its hold state, by reading this from an array that acts as
a table for all the PEs. The hold states are initially set to 0 for all
cores to indicate that the executing core should continue polling.
To prevent the secondary CPUs from interfering with the platform's
initialization, they are only updated by the primary CPU once the cold
boot sequence has completed and fpga_pwr_domain_on(mpidr) is called.
The polling target CPU will then read 1 (which indicates that it should
branch to the warm reset entrypoint) and then jump to that address
rather than continue polling.

In addition to the initial polling behaviour of the secondary CPUs
before their warm boot reset sequence, they are also placed in a
low-power wfe() state at the end of each poll; accordingly, the PSCI
fpga_pwr_domain_on(mpidr) function also signals an event to all cores
(after updating the target CPU's hold entry) to wake them from this
state, allowing any secondary CPUs that are still polling to check
their hold state again.
This method is in accordance with both the PSCI and Linux kernel
recommendations, as the lessened overhead reduces the energy
consumption associated with the busy-loop.

The table of hold entries is implemented by a global array as shared SRAM
(which is used by other platforms in similar implementations) is not
available on the FPGA images.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
      7ee4db6e
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow · 5cfe699f
      Oliver Swede authored 
      This makes use of the PRELOADED_BL33_BASE flag to indicate to BL31 that
the BL33 payload (kernel) has already been loaded and resides in memory;
BL31 will then jump to the non-secure address.

For this port the BL33 payload is the Linux kernel, and in accordance
with the pre-kernel setup requirements (as specified in the `Booting
AArch64 Linux' documentation:
https://www.kernel.org/doc/Documentation/arm64/booting.txt

),
this change also sets up the primary CPU's registers x0-x3 so they are
the expected values, which includes the address of the DTB at x0.

An external linker script is currently required to combine BL31, the
BL33 payload, and any other software images to create an ELF file that
can be uploaded to the FPGA board along with the bit file. It therefore
has dependencies on the value of PRELOADED_BL33_BASE (kernel base) and
the DTB base (plus any other relevant base addresses used to
distinguish the different ELF sections), both of which are set in this
patch.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: If7ae8ee82d1e09fb05f553f6077ae13680dbf66b
      5cfe699f
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image · 536d906a
      Oliver Swede authored 
      

This adds the minimal functions and definitions to create a basic
BL31 port for an initial FPGA image, in order for the port to be
uploaded to one the FPGA boards operated by an internal group within
Arm, such that BL31 runs as a payload for an image.

Future changes will enable the port for a wide range of system
configurations running on the FPGA boards to ensure compatibility with
multiple FPGA images.

It is expected that this will replace the FPGA fork of the Linux kernel
bootwrapper by performing similar secure-world initialization and setup
through the use of drivers and other well-established methods, before
passing control to the kernel, which will act as the BL33 payload and
run in EL2NS.

This change introduces a basic, loadable port with the console
initialized by setting the baud rate and base address of the UART as
configured by the Zeus image.

It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
      536d906a
    • Yann Gautier's avatar
      stm32mp1: use stm32mp_get_ddr_ns_size() function · 5813e6ed
      Yann Gautier authored 
      

Instead of using dt_get_ddr_size() and withdrawing the secure and shared
memory areas, use stm32mp_get_ddr_ns_size() function.

Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      5813e6ed
    • Yann Gautier's avatar
      stm32mp1: set XN attribute for some areas in BL2 · 9c52e69f
      Yann Gautier authored 
      

DTB and BL32 area should not be set as executable in MMU during BL2
execution, hence set those areas as MT_RO_DATA.

Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      9c52e69f
    • Yann Gautier's avatar
      stm32mp1: dynamically map DDR later and non-cacheable during its test · 84686ba3
      Yann Gautier authored 
      

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      84686ba3
    • Yann Gautier's avatar
      stm32mp1: add a function to get non-secure DDR size · e6cc3ccf
      Yann Gautier authored 
      

This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.

Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      e6cc3ccf
  11. 25 Mar, 2020 2 commits
  13. 23 Mar, 2020 6 commits
    • Varun Wadekar's avatar
      Tegra194: se: increase max. operation timeout to 1 second · 3d1cac96
      Varun Wadekar authored 
      

This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operation might take more time than the previous timeout value
of 100ms.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I0012448ba372a8bb0e156df7dfe49d7de6d21a68
      3d1cac96
    • Olivier Deprez's avatar
      spmd: skip loading of secure partitions on pre-v8.4 platforms · c33ff198
      Olivier Deprez authored 
      

When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.
Signed-off-by: default avatarOlivier Deprez <olivier.deprez@arm.com>
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df
      c33ff198
    • Yann Gautier's avatar
      plat/st: correctly check pwr-regulators node · e9d1e5af
      Yann Gautier authored 
      

This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
 (warning) Identical condition 'node<0', second condition is always false

The second test has to check variable pwr_regulators_node.

Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      e9d1e5af
    • Yann Gautier's avatar
      plat/st: correct static analysis tool warning · cd4941de
      Yann Gautier authored 
      

Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
 symbol 'fdt_get_node_parent_address_cells' was not declared.
 Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
 symbol 'fdt_get_node_parent_size_cells' was not declared.
 Should it be static?

As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.

Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      cd4941de
    • Igor Opaniuk's avatar
      plat: imx: imx8qx: provide debug uart num as build param · 30617cca
      Igor Opaniuk authored 
      1. This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.

Also for Colibri i.MX8QXP different pinmux configuration is applied
for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX.

2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit
for i.MX8QM 98a69dfd

("plat: imx: imx8qm: apply clk/pinmux
configuration for DEBUG_CONSOLE")).

Usage:
$ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31
Signed-off-by: default avatarIgor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
      30617cca
    • Andre Przywara's avatar
      allwinner: H6: Fix GPIO and CCU memory map addresses · 5fac0d32
      Andre Przywara authored 
      

The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.

The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.

The issue was found and reported by Github user "armlabs".

Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      5fac0d32
  15. 22 Mar, 2020 9 commits