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  1. 01 Apr, 2021 1 commit
  3. 03 Mar, 2021 1 commit
  5. 24 Feb, 2021 1 commit
  7. 12 Jan, 2021 2 commits
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  11. 04 Jan, 2021 3 commits
  13. 15 Dec, 2020 4 commits
  15. 10 Dec, 2020 2 commits
  17. 08 Dec, 2020 2 commits
    • Ravi Patel's avatar
      zynqmp: pm: Update flags in common clk divisor node · c8f62536
      Ravi Patel authored 
      

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
 Consider a case of nand_ref clock which has 2 divisor and 1 mux.
 The frequency of mux clock is 1500MHz and default value of div1 and
 div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
 When driver requests 80MHz for nand_ref clock, clock framework will
 adjust the div2 value to 1 (setting div2 value 2 results final clock
 to 50MHz which is more inaccurate compare to 100Mhz) which results
 final clock to 100MHz.
 Ideally the value of div1 and div2 should be updated to 19 and 1
 respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.
Signed-off-by: default avatarRavi Patel <ravi.patel@xilinx.com>
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
      c8f62536
    • Siva Durga Prasad Paladugu's avatar
      zynqmp: pm_api_clock: Copy only the valid bytes · f2afaad0
      Siva Durga Prasad Paladugu authored 
      

This patches copies only the valid part of string and
avoids filling junk at the end.
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7
      f2afaad0
  19. 07 Dec, 2020 2 commits
  21. 04 Dec, 2020 1 commit
  23. 12 Nov, 2020 3 commits
  25. 09 Oct, 2020 1 commit
    • Jimmy Brisson's avatar
      Don't return error information from console_flush · 831b0e98
      Jimmy Brisson authored 
      

And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.

Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      831b0e98
  27. 30 Mar, 2020 1 commit
  29. 25 Feb, 2020 1 commit
  31. 30 Jan, 2020 1 commit
  33. 24 Jan, 2020 1 commit
  35. 23 Jan, 2020 1 commit
  37. 22 Jan, 2020 1 commit
  39. 15 Jan, 2020 9 commits
  41. 07 Jan, 2020 1 commit
    • Rajan Vaja's avatar
      zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list · 20fdf0b0
      Rajan Vaja authored 
      

CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as parent of other clocks.

WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock).
If CLK_TOPSW_LSBUS is not registered, CCF would not recognize
that clock and hence rate of WDT clock would be calculated to
be 0 by CCF(as parent rate is considered 0).

So it is necessary to allow registration of CLK_TOPSW_LSBUS
clock.
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc
      20fdf0b0