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  1. 24 Feb, 2021 1 commit
  3. 12 Jan, 2021 2 commits
  5. 11 Jan, 2021 1 commit
  7. 04 Jan, 2021 3 commits
  9. 15 Dec, 2020 4 commits
  11. 10 Dec, 2020 2 commits
  13. 08 Dec, 2020 2 commits
    • Ravi Patel's avatar
      zynqmp: pm: Update flags in common clk divisor node · c8f62536
      Ravi Patel authored 
      

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
 Consider a case of nand_ref clock which has 2 divisor and 1 mux.
 The frequency of mux clock is 1500MHz and default value of div1 and
 div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
 When driver requests 80MHz for nand_ref clock, clock framework will
 adjust the div2 value to 1 (setting div2 value 2 results final clock
 to 50MHz which is more inaccurate compare to 100Mhz) which results
 final clock to 100MHz.
 Ideally the value of div1 and div2 should be updated to 19 and 1
 respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.
Signed-off-by: default avatarRavi Patel <ravi.patel@xilinx.com>
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
      c8f62536
    • Siva Durga Prasad Paladugu's avatar
      zynqmp: pm_api_clock: Copy only the valid bytes · f2afaad0
      Siva Durga Prasad Paladugu authored 
      

This patches copies only the valid part of string and
avoids filling junk at the end.
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7
      f2afaad0
  15. 07 Dec, 2020 2 commits
  17. 04 Dec, 2020 1 commit
  19. 12 Nov, 2020 3 commits
  21. 09 Oct, 2020 1 commit
    • Jimmy Brisson's avatar
      Don't return error information from console_flush · 831b0e98
      Jimmy Brisson authored 
      

And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.

Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      831b0e98
  23. 30 Mar, 2020 1 commit
  25. 25 Feb, 2020 1 commit
  27. 30 Jan, 2020 1 commit
  29. 24 Jan, 2020 1 commit
  31. 23 Jan, 2020 1 commit
  33. 22 Jan, 2020 1 commit
  35. 15 Jan, 2020 9 commits
  37. 07 Jan, 2020 3 commits
    • Rajan Vaja's avatar
      zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list · 20fdf0b0
      Rajan Vaja authored 
      

CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as parent of other clocks.

WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock).
If CLK_TOPSW_LSBUS is not registered, CCF would not recognize
that clock and hence rate of WDT clock would be calculated to
be 0 by CCF(as parent rate is considered 0).

So it is necessary to allow registration of CLK_TOPSW_LSBUS
clock.
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc
      20fdf0b0
    • Mounika Grace Akula's avatar
      zynqmp: pm: Add LPD WDT clock to the pm_clock structure · b3ce966a
      Mounika Grace Akula authored 
      

This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.

Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.
Signed-off-by: default avatarMounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
      b3ce966a
    • Mirela Simonovic's avatar
      zynqmp: pm: Fix clock models and IDs of GEM-related clocks · 06ad9803
      Mirela Simonovic authored 
      

GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):

- CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and
 the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this
 clock is newly introduced in this patch.

- CLK_GEM0_REF models the clock mux that selects the reference clock
 for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This
 mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL.
 Note that the routing of external clock to the mux is not modelled
 and is assumed to be configured by the FSBL if required, and not
 changeable at runtime. The ID of this clock is introduced in this patch.

- CLK_GEM0_TX models clock with only a gate that is controlled via
 bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is
 CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID
 value of CLK_GEM0_REF. This is done in order to fix the clock models
 and incorrect binding without requiring to change device-tree (binding
 of clock IDs to GEM interface).

- CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT
 bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced
 from external RGMII PHY (via MIO or EMIO). We do not model the whole
 clock path to the Rx gate, since this is configured by the FSBL and
 never changed at runtime (and there is no mechanism to change the
 path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the
 previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX
 were swapped in device tree, so by fixing the IDs this way there is no
 need for device tree fix.

Rates of the external RX/TX clocks can be specified in device tree if
needed. Right now, that's not necessary because Tx clock is sourced
from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas
the Rx clock is sourced from external reference and the driver never
attempts to get/get clock rate (only to enable it). If this changes in
future, ATF clock model doesn't need to be changed. Instead, the clock
rates for gem0_tx_ext and gem0_rx_ext have to be specified in device
tree.
Signed-off-by: default avatarMirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: default avatarWill Wong <will.wong@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79
      06ad9803