- 29 Jan, 2021 1 commit
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Madhukar Pappireddy authored
For SoCs which do not implement RAS, use DSB as a barrier to synchronize pending external aborts at the entry and exit of exception handlers. This is needed to isolate the SErrors to appropriate context. However, this introduces an unintended side effect as discussed in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440 A summary of the side effect and a quick workaround is provided as part of this patch and summarized here: The explicit DSB at the entry of various exception vectors in BL31 for handling exceptions from lower ELs can inadvertently trigger an SError exception in EL3 due to pending asyncrhonouus aborts in lower ELs. This will end up being handled by serror_sp_elx in EL3 which will ultimately panic and die. The way to workaround is to update a flag to indicate if the exception truly came from EL3. This flag is allocated in the cpu_context structure. This is not a bullet proof solution to the problem at hand because we assume the instructions following "isb" that help to update the flag (lines 100-102 & 139-141) execute without causing further exceptions. Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 28 Jan, 2021 2 commits
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Sandrine Bailleux authored
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André Przywara authored
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- 27 Jan, 2021 5 commits
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Lauren Wehrmeister authored
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Nikos Nikoleris authored
The value of stdout-path is a string and as a result, we can't use a label as a reference to the serial0 node. This change fixes the stdout-path property for N1SDP, Morello and TC0 by pointing to the right alias. Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Change-Id: I3d403389a424569be56327fab4140fec06f96d37
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Madhukar Pappireddy authored
* changes: doc: maintainers: add scmi server drivers: move scmi-msg out of st
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Jimmy Brisson authored
This bug manifests itself as a segfault triggered by a double-free. I noticed that right before the double-free, the sk list contained 2 elements with the same address. (gdb) p sk_X509_EXTENSION_value(sk, 1) $34 = (X509_EXTENSION *) 0x431ad0 (gdb) p sk_X509_EXTENSION_value(sk, 0) $35 = (X509_EXTENSION *) 0x431ad0 (gdb) p sk_X509_EXTENSION_num(sk) $36 = 2 This caused confusion; this should never happen. I figured that this was caused by a ext_new_xxxx function freeing something before it is added to the list, so I put a breakpoint on each of them to step through. I was suprised to find that none of my breakpoints triggered for the second element of the iteration through the outer loop just before the double-free. Looking through the code, I noticed that it's possible to avoid doing a ext_new_xxxx, when either: * ext->type == NVCOUNTER and ext->arg == NULL * ext->type == HASH and ext->arg == NULL and ext->optional == false So I put a breakpoint on both. It turns out that it was the HASH version, but I added a fix for both. The fix for the Hash case is simple, as it was a mistake. The fix for the NVCOUNTER case, however, is a bit more subtle. The NVCOUNTER may be optional, and when it's optional we can skip it. The other case, when the NVCOUNTER is required (not optinal), the `check_cmd_params` function has already verified that the `ext->arg` must be non-NULL. We assert that before processing it to covert any possible segfaults into more descriptive errors. This should no longer cause double-frees by adding the same ext twice. Change-Id: Idae2a24ecd964b0a3929e6193c7f85ec769f6470 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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Manish V Badarkhe authored
The certification tool creates all the certificates mentioned statically in the code rather than taking explicit certificate requests from the command line parameters. Code is optimized to avoid unnecessary attempts to create non-requested certificates. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I78feac25bc701bf8f08c6aa5a2e1590bec92d0f2
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- 26 Jan, 2021 2 commits
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Manish Pandey authored
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Sandrine Bailleux authored
* changes: plat/qemu: Use RNDR in stack protector Makefile: Add FEAT_RNG support define Define registers for FEAT_RNG support
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- 25 Jan, 2021 3 commits
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Lauren Wehrmeister authored
* changes: Makefile: Fix ${FIP_NAME} to be rebuilt only when needed Makefile: Do not mark file targets as .PHONY target
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Manish Pandey authored
Merge "plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF" into integration
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Peng Fan authored
Add maintainer entry for scmi server Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I673d7395a8cea3b553832e330c8a8ce37f8c2a5c
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- 24 Jan, 2021 1 commit
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Madhukar Pappireddy authored
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- 22 Jan, 2021 3 commits
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Madhukar Pappireddy authored
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Olivier Deprez authored
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Yann Gautier authored
The base address of UART peripheral should be given in R0, not in R1. Otherwise the console_stm32_core_flush issues an assert message. This issue was highlighted with recent changes in console flush functions. Change-Id: Iead01986fdbbf30ad2fd9fa515a1d2b611b4e591 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 21 Jan, 2021 3 commits
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Madhukar Pappireddy authored
* changes: libc/snprintf: use macro to reduce duplicated code libc/snprintf: add support to print "%" character libc/printf: add support to print "%" character
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Zelalem authored
To avoid a potential out-of-bounds access, check whether a device exists on a channel before calling the corresponding clone function. Signed-off-by: Zelalem <zelalem.aweke@arm.com> Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b
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David Horstmann authored
Fix some typos and misspellings in TF-A documentation. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
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- 20 Jan, 2021 13 commits
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Manish Pandey authored
* changes: plat/arm/css/sgi: Fix assert expression issue plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue
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Madhukar Pappireddy authored
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Ming Huang authored
Violation of MISRA-C Rule 14.4 Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4
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Ming Huang authored
The issue is that, when interrupt is triggered and RAS handler is entered, after interrupt handler finishes, TF-A will re-enter bl32 and then crash. sdei_dispatch_event() may return failing result in some cases, for example kernel may not have registered a handler or RAS event may happen early during boot. We restore the NS context when sdei_dispatch_event() returns failing result. error log : Received delegated event X0 : 0xC4000061 X1 : 0x0 X2 : 0x0 X3 : 0x0 Received event - 0xC4000061 on cpu 0 UnRecognized Event - 0xC4000061 Failed delegated event 0xC4000061, Status Invalid Parameter Unhandled Exception in EL3. x30 = 0x000000000401f700 x0 = 0xfffffffffffffffe x1 = 0xfffffffffffffffe x2 = 0x00000000600003c0 Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f
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Manish Pandey authored
* changes: doc: renesas: Update RZ/G2 code owner list plat: renesas: rzg: DT memory node enhancements renesas: rzg: emmc: Enable RZ/G2M support plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support drivers: renesas: rzg: Add HiHope RZ/G2M board support tools: renesas: Add tool support for RZ/G2 platforms
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Madhukar Pappireddy authored
* changes: marvell: uart: a3720: Fix macro name for 6th bit of Status Register marvell: uart: a3720: Implement console_a3700_core_getc
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Madhukar Pappireddy authored
* changes: qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller qemu/qemu_sbsa: topology is different from qemu so add handling qemu/common : change DEVICE2 definition for MMU qemu/aarch64/plat_helpers.S : calculate the position shift
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Jagadeesh Ujja authored
Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF. Issue : The Linux prompt hangs when all the cores in a cluster are turned OFF and we try to turn ON a core in that cluster. Previously when TF-A turns ON a core, TF-A first turns ON the redistributor followed by the core. This did not match the flow when turning OFF a core, as TF-A did not turn OFF redistributor when the corresponding core[s] are disabled. This hang is resolved by disabling redistributor as cores are disabled, keeping them in sync. Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Change-Id: Ifd04fdcfd47b45e00f874f15b098471883d023f0
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Rajan Vaja authored
Some switch cases uses same operation. So, club switch cases which uses same operation and remove duplicate code. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
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Heyi Guo authored
Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one character to buffer, and then increase character counter by one in one single statement, so that 4 similar code pieces can be cleaned. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1
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Heyi Guo authored
Enable snprintf()/vsnprintf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8
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Heyi Guo authored
Enable printf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622
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Peng Fan authored
Make the scmi-msg driver reused by others. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124
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- 19 Jan, 2021 7 commits
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Graeme Gregory authored
This allows PSCI in TF-A to signal platform power states to QEMU via a controller in secure space. This required a sbsa-ref specific version of PSCI functions for the platform. Also adjusted the MMU range to also include the new EC. Add a new MMU region for the embedded controller and increase the size of xlat tables by one for the new region. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee
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Graeme Gregory authored
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512 cores in upto 64 clusters. Implement a qemu_sbsa specific topology file and increase the BL31_SIZE to accommodate the bigger table sizes. Change platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so plat_helpers.S calculates correct result. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
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Graeme Gregory authored
DEVICE2 is not currently used on qemu platform but is needed for a future patch for qemu_sbsa platform. Change its definition to RW and add it to all levels of arm-tf similar to DEVICE1 definition. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf
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Graeme Gregory authored
Rather than re-create this file in multiple qemu variants instead caclulate the shift needed to convert MPIDR to position. Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h for both qemu and qemu_sbsa to enable this calculation. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
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Madhukar Pappireddy authored
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Tomas Pilar authored
When getting a stack protector canary value, check if cpu supports FEAT_RNG and use that. Fallback to old method of using a (hardcoded value ^ timer). Signed-off-by: Tomas Pilar <tomas@nuviainc.com> Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725
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Ahmad Fatoum authored
The Linux Automation MC-1 is a SBC built around the Octavo Systems OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and PMIC. The board has eMMC and a SD slot for storage. The SDRAM calibration values are taken as is from the DKx boards, which seem to be suitable for operation at German room temperature. This is deemed ok for now, but for use in the field, the SiP will likely need to have its timings determined in a climate chamber. Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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