- 10 May, 2019 4 commits
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Soby Mathew authored
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Antonio Niño Díaz authored
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Antonio Niño Díaz authored
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kenny liang authored
- Add basic platform setup - Add generic CPU helper functions - Add delay timer platform implementation - Use TI 16550 uart driver Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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- 09 May, 2019 4 commits
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Leonard Crestez authored
The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but it's also applicable to imx8m. This fixes U-Boot not printing commit hash on 8m with upstream TF-A. Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Antonio Nino Diaz authored
I'm giving full maintainership of the Raspberry Pi 3 platform port to Paul. I'm also leaving the GXBB maintainership to Andre, who is also happy to pass it on to someone else who is more interested in it. Change-Id: Ieb2212f5fc11ebde9fc0c857e9e305d691d4ee3f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Niño Díaz authored
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John Tsichritzis authored
Pointer authentication is supported only in AArch64. A relevant check is added for that in the Makefile. Change-Id: I021ba65a9bd5764fd33292bee42617015e04a870 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 08 May, 2019 6 commits
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Soby Mathew authored
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Antonio Niño Díaz authored
* changes: plat: imx8mq: Only keep IRQ 32 unmasked plat: imx8mq: gpc: Enable all power domain by default
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Soby Mathew authored
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John Tsichritzis authored
1) One space was missing from the indentation and, hence, rendering error was generated in the user guide. 2) Partially reword Pointer Authentication related info. Change-Id: Id5e65d419ec51dd7764f24d1b96b6c9942d63ba4 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Leonard Crestez authored
Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible by 32. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Change-Id: I286b925eead89218cfeddd82f53a634f3447d212
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Leonard Crestez authored
This is similar to imx8mm and allows uboot to run fastboot over USB otg. There is a different set of power domains on 8mq but same bits covers all off them. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d
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- 07 May, 2019 3 commits
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Soby Mathew authored
* changes: Workaround for cortex-A76 errata 1286807 Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
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Soby Mathew authored
The workaround for Cortex-A76 errata #1286807 is implemented in this patch. Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are added to the Cortex-A76 cpu specific file. The workarounds are disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I70474927374cb67725f829d159ddde9ac4edc343 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 03 May, 2019 4 commits
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Soby Mathew authored
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John Tsichritzis authored
This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Soby Mathew authored
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Alexei Fedorov authored
This patch is a preparation for the subsequent changes in SMMUv3 driver. It introduces a new "smmuv3_poll" function and replaces inline functions for accessing SMMU registers with mmio read/write operations. Also the infinite loop for the poll has been replaced with a counter based timeout. Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 02 May, 2019 4 commits
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Soby Mathew authored
* changes: rockchip: Disable binary generation for all SoCs. build_macros: Add mechanism to prevent bin generation.
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Christoph Müllner authored
All supported Rockchip SoCs (RK3288, RK3328, RK3368 and RK3399) have non-continuous memory areas in the linker script with a huge gap between them. This results in extremely padded binary images with a size of about 4 GiB. E.g. on the RK3399 we have the following memory areas (and base addresses): RAM (0x1000), SRAM (0xFF8C0000), and PMUSRAM (0xFF3B0000). Consumers of the TF-A project (e.g. coreboot or U-Boot) therefore use the ELF image instead, which has a size of a few hundred kBs. In order to prevent the generation of a huge and useless file, this patch disables the binary generation for all affected Rockchip SoCs. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I4ac65bdf1e598c3e1a59507897d183aee9a36916
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Christoph Müllner authored
On certain platforms it does not make sense to generate TF-A binary images. For example a platform could make use of serveral memory areas, which are non-continuous and the resulting binary therefore would suffer from the padding-bytes. Typically these platforms use the ELF image. This patch introduces a variable DISABLE_BIN_GENERATION, which can be set to '1' in the platform makefile to prevent the binary generation. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I62948e88bab685bb055fe6167d9660d14e604462
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Antonio Niño Díaz authored
* changes: rockchip: Allow console device to be set by DTB. rockchip: Add params_setup to RK3328. rockchip: Streamline and complete UARTn_BASE macros.
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- 01 May, 2019 3 commits
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Christoph Müllner authored
Currently the compile-time constant PLAT_RK_UART_BASE defines which UART is used as console device. E.g. on RK3399 it is set to UART2. That means, that a single bl31 image can not be used for two boards, which just differ on the UART console. This patch addresses this limitation by parsing the "stdout-path" property from the "chosen" node in the DTB. The expected property string is expected to have the form "serialN:XXX", with N being either 0, 1, 2, 3 or 4. When the property is found, it will be used to override PLAT_RK_UART_BASE. Tested on RK3399-Q7, with a stdout-path of "serial0:115200n8". Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: Iafe1320e77ab006c121f8d52745d54cef68a48c7
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Christoph Müllner authored
params_setup.c provides the function params_early_setup, which takes care of parsing ATF parameters (bl31_plat_param array, fdt or coreboot table). As params_early_setup is defined as weak symbol in bl31_plat_setup.c, providing a platform-specific bl31_plat_setup implementation is optional. This patch adds the rockchip-common params_setup.c to the sources for RK3328. This streamlines the parameter handling for all supported rockchip SoCs. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I071c03106114364ad2fc408e49cc791fe5b35925
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Christoph Müllner authored
In order to set the UART base during bootup in common code of plat/rockchip, we need to streamline the way the UART base addresses are defined and add the missing definitions and mappings. This patch does so by following the pattern UARTn_BASE, which is already in use on RK3399 and RK3328. The numbering itself is derived from the upstream Linux DTS files of the individual SoCs. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f
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- 30 Apr, 2019 6 commits
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Julius Werner authored
This patch updates the contribution guidelines to refer to the new binary repository. Change-Id: I898dc58973be91c3f87be53a755269fca2e93174 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Soby Mathew authored
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Soby Mathew authored
* changes: juno: Add security sources for tsp-juno Add support for default stack-protector flag
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Louis Mayencourt authored
Security sources are required if stack-protector is enabled. Change-Id: Ia0071f60cf03d48b200fd1facbe50bd9e2f8f282 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
The current stack-protector support is for none, "strong" or "all". The default use of the flag enables the stack-protection to all functions that declare a character array of eight bytes or more in length on their stack. This option can be tuned with the --param=ssp-buffer-size=N option. Change-Id: I11ad9568187d58de1b962b8ae04edd1dc8578fb0 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Andrew F. Davis authored
The MSMC port defines were added to help in the case when some ports are not connected and have no cores attached. We can get the same functionality by defined the number of cores on that port to zero. This simplifies several code paths, do this here. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a
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- 29 Apr, 2019 6 commits
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Soby Mathew authored
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Soby Mathew authored
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Soby Mathew authored
* changes: fdts: Fix DTC warnings for STM32MP1 platform docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable stm32mp1: Add Avenger96 board support
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Soby Mathew authored
* changes: ti: k3: common: Mark sections for AM65x coherency workaround ti: k3: common: Allow USE_COHERENT_MEM for K3 ti: k3: common: Fix RO data area size calculation ti: k3: common: Remove unused STUB macro
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Antonio Niño Díaz authored
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Antonio Niño Díaz authored
* changes: plat: marvell: do not rely on argument passed via smc plat: marvell: sip: make sure that comphy init will use correct address
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