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* changes:
  allwinner: Split native and SCPI-based PSCI implementations
  allwinner: psci: Improve system shutdown/reset sequence
  allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback
  allwinner: Separate code to power off self and other CPUs

* changes:
  marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
  marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU
  marvell: uart: a3720: Fix comments in console_a3700_core_init() function

This reverts commit bedb13f5.
SIMD context is now saved in S-EL2 as opposed to EL3, see commit:
https://review.trustedfirmware.org/c/hafnium/hafnium/+/8321

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic81416464ffada1a6348d0abdcf3adc7c1879e61

Rename rd_n1e1_edge_scmi_plat_info array to plat_rd_scmi_info as the
same array is used to provide SCMI platform info across mulitple RD
platforms and is not resitricted to only RD-N1 and RD-E1 platforms.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I42ba33e0afa3003c731ce513c6a5754b602ec01f

Add blank lines before lists and code example.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I901646e0be74227af983079d0cbe05c6a217fab6

TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so wait at least 3ms
before flushing TX FIFO.

If WTMI firmware transmitted something via UART before TF-A was booted,
some characters may still wait in TX FIFO when TF-A is initializing UART
driver. So wait at least 3ms to ensure that HW has enough time to transmit
all characters waiting in TX FIFO.

This fixes an issue where sometimes characters transmitted on UART by our
custom WTMI image are lost.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19

Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to
wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720
CPU is 600 MHz and in this case delay loop would take just 2 times more,
which is not a problem.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2

The delay loop executes 3 instructions. These 3 instructions are executed
in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield
approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX
FIFO to be empty.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f

NXP specifc macro SET_NXP_MAKE_FLAG is added.

NXP has pool of multiple IPs. This macro helps:
- In soc.mk, this macro help the selected IP source files to be included
  for that SoC.
  -- The set of IPs required for one NXP SoC is different to the set of IPs
     required by another NXP SoC.

- For the same SoC,
  -- For one feature, the IP may be required in both BL2 and BL31.
  -- Without the above feature, that IP may be required in one.
     This macro help in selecting the inclusion of source and header files to:
     --- BL2 only
     --- BL31 only
     --- COMM (used by BL2 and BL31)
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cdb13b89aa815fc5219cf8bfb9666d0a9f78765

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8ed58ec5f97e05d91451020a2739464bb8e428b3

* changes:
  libc: Import strtoull from FreeBSD project
  libc: Import strtoll from FreeBSD project
  libc: Import strtoul from FreeBSD project
  libc: Import strtol from FreeBSD project

Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we will actually only ever request 16 bytes, as this is what
the hardware implements. Out of this, we only need at most 64 bits for
the canary.

In preparation for the introduction of the SMCCC TRNG interface, we
can simplify this Juno specific interface by making it compatible with
the generic one: We just deliver 64 bits of entropy on each call.
This reduces the complexity of the code. As the raw entropy register
readouts seem to be biased, it makes sense to do some conditioning
inside the juno_getentropy() function already.
Also initialise the TRNG hardware, if not already done.

Change-Id: I11b977ddc5417d52ac38709a9a7b61499eee481f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The Trusted Random Number Generator service is using the standard SMC
service dispatcher, running in BL31. For that reason we list the files
implementing the service in bl31.mk.
However when building for a 32-bit TF-A runtime, sp_min.mk is the
Makefile snippet used, so we have to add the files into there as well.

This fixes 32-bit builds of platforms that provide the TRNG service.

Change-Id: I8be61522300d36477a9ee0a9ce159a140390b254
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Update TZC base address to align with the recent changes in the platform
memory map.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a

The code to check for the presence of the TRNG service relies on
toolchain garbage collection, which is not enabled with -O0.

Add #ifdef guards around the call to the TRNG service handler to
cover builds without optimisation as well.

Change-Id: I08ece2005ea1c8fa96afa13904a851dec6b24216
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

* changes:
  plat/arm: fvp: Protect GICR frames for fused/unused cores
  doc: Build option to protect GICR frame
  plat/arm: fvp: Do not map GIC region in BL1 and BL2

Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.

This opens up the security hole where the active core can write
the GICR frame of fused/inactive core. To avoid this issue, disable
the GICR frame of all inactive cores as below:

1. After primary CPU boots up, map GICR region of all cores as
   read-only.
2. After primary CPU boots up, map its GICR region as read-write
   and initialize its redistributor interface.
3. After secondary CPU boots up, map its GICR region as read-write
   and initialize its redistributor interface.
4. All unused/fused core's redistributor regions remain read-only and
   write attempt to such protected regions results in an exception.

As mentioned above, this patch offers only the GICR memory-mapped
region protection considering there is no facility at the GIC IP
level to avoid writing the redistributor area.

These changes are currently done in BL31 of Arm FVP and guarded under
the flag 'FVP_GICR_REGION_PROTECTION'.

As of now, this patch is tested manually as below:
1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core.
2. Verify data abort triggered by manually updating the ‘GICR_CTLR’
   register of core 1’s(fused) redistributor from core 0(active).

Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.

Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memory regions in the
future.

Retains mapping of CCN interconnect region in BL1 and BL2
overlapped with the GIC memory region.

Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

This allows Matterhorn cores to operate at their optimal OPPs.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116

The structure has been modified to specify the memory
size in bytes instead of Gigabytes.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I3384677d79af4f3cf55d3c353b6c20bb827b5ae7

This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.

Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is
wrong. This field is from bit 16 to 23.

Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The NUM_APID value was derived from kernel device tree sources, but I
made a conversion mistake: the amount of bytes in the APID map is the
total size of the "core" register range (0x1100) minus the offset of the
APID map in that range (0x900). This is of course 0x1100 - 0x900 = 0x800
and not 0x200, so the amount of 4-byte integers it can fit is not 0x80
but 0x200. Fix this and make the math more explicit so it can be more
easily factored out and adjusted if that becomes necessary for a future
SoC.

Also fix a dangerous typo in REG_APID_MAP() where the macro would
reference a random variable `i` rather than its argument (`apid`), and
we just got lucky that the only caller in the current code happened to
pass in a variable called `i` as that argument.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I049dd044fa5aeb65be0e7b12150afd6eb4bac0fa