- 28 Jun, 2018 6 commits
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Andre Przywara authored
The DRAM controller supports up to 4GB of DRAM, and there are actually boards out there where we can use at least 3GB of this. Relax the PSCI entry point check, to be not restricted to 2GB of DRAM. Signed-off-by:Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
The "#ifdef SUNXI_SPC_BASE" guard was meant to allow the build on SoCs without a Secure Peripherals Controller, so that we skip that part of the security setup. But in the current position this will trigger a warning about an unused variable. Simply move the guard one line up to cover the variable as well. Signed-off-by: -
Andre Przywara authored
The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more obvious by changing the log level to "VERBOSE" and so avoiding it to be printed in a normal (even debug) build. Reported-by:
Samuel Holland <samuel@sholland.org> Signed-off-by:
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Andre Przywara authored
The relative VER_REG *offset* is the same across all known SoCs, so we can define this offset near it's user. Remove it from the memory map. Reported-by:
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Andre Przywara authored
Some code in sunxi_common.c requires symbols defined in sunxi_private.h, so add the header to that file. It was included via another header before, but let's make this explicit. Reported-by:
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Amit Singh Tomar authored
This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along side BL31 image. ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS) as an input using the 'SPD=<dispatcher name>' option during bl31 build. Signed-off-by:Amit Singh Tomar <amittomer25@gmail.com>
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- 15 Jun, 2018 5 commits
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Andre Przywara authored
Some peripherals are TrustZone aware, so they need to be configured to be accessible from non-secure world, as we don't need any of them being exclusive to the secure world. This affects some clocks, DMA channels and the Secure Peripheral Controller (SPC). The latter controls access to most devices, but is not active unless booting with the secure boot fuse burnt. Signed-off-by: -
Samuel Holland authored
The reset vector entry point is preserved across CPU resets, so it only needs to be set once at boot. Hotplugged CPUs are not actually powered down, but are put in a wfi with the GIC disconnected. With this commit, Linux is able to enable, hotplug and use all four CPUs. Signed-off-by:
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Samuel Holland authored
sun50i_cpu_on will be used by the PSCI implementation to initialize secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by PSCI directly, because it is not possible for a CPU to use this function to power itself down. Power cannot be shut off until the outputs are clamped, and MMIO does not work once the outputs are clamped. But at least CPU0 can shutdown the other cores early in the BL31 boot process and before shutting down the system. Signed-off-by:
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Samuel Holland authored
The Allwinner A64 SoC is quite popular on single board computers. It comes with four Cortex-A53 cores in a singe cluster and the usual peripherals for set-top box/tablet SoC. The ATF platform target is called "sun50i_a64". [Andre: adapted to amended directory layout, removed unneeded definitions ] Signed-off-by:
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Samuel Holland authored
This platform supports Allwinner's SoCs with ARMv8 cores. So far they all sport a single cluster of Cortex-A53 cores. "sunxi" is the original code name used for this platform, and since it appears in the Linux kernel and in U-Boot as well, we use it here as a short file name prefix and for identifiers. This port includes BL31 support only. U-Boot's SPL takes the role of the primary loader, also doing the DRAM initialization. It then loads the rest of the firmware, namely ATF and U-Boot (BL33), then hands execution over to ATF. This commit includes the basic platform code shared across all SoCs. There is no platform.mk yet. [Andre: moved files into proper directories, supported RESET_TO_BL31, various clean ups and simplifications ] Signed-off-by:
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