1. 10 Apr, 2019 2 commits
  2. 08 Apr, 2019 1 commit
  3. 03 Apr, 2019 2 commits
  4. 01 Apr, 2019 2 commits
  5. 21 Mar, 2019 1 commit
    • John Tsichritzis's avatar
      ROMLIB bug fixes · ae2e01b8
      John Tsichritzis authored
      
      
      Fixed the below bugs:
      1) Bug related to build flag V=1: if the flag was V=0, building with
      ROMLIB would fail.
      2) Due to a syntax bug in genwrappers.sh, index file entries marked as
      "patch" or "reserved" were ignored.
      3) Added a prepending hash to constants that genwrappers is generating.
      4) Due to broken dependencies, currently the inclusion functionality is
      intentionally not utilised. This is why the contents of romlib/jmptbl.i
      have been copied to platform specific jmptbl.i files. As a result of the
      broken dependencies, when changing the index files, e.g. patching
      functions, a clean build is always required. This is a known issue that
      will be fixed in the future.
      
      Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa
      Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      ae2e01b8
  6. 19 Mar, 2019 1 commit
    • Antonio Nino Diaz's avatar
      xlat_tables_v2: Revert recent changes to remove recursion · f253645d
      Antonio Nino Diaz authored
      This commit reverts the following commits:
      
      - c54c7fc3 ("xlat_tables_v2: print xlat tables without recursion")
      - db8cac2d ("xlat_tables_v2: unmap region without recursion.")
      - 0ffe2692
      
       ("xlat_tables_v2: map region without recursion.")
      
      This was part of PR#1843.
      
      A problem has been detected in one of our test run configurations
      involving dynamic mapping of regions and it is blocking the next
      release. Until the problem can be solved, it is safer to revert
      the changes.
      
      Change-Id: I3d5456e4dbebf291c8b74939c6fb02a912e0903b
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      f253645d
  7. 14 Mar, 2019 5 commits
  8. 13 Mar, 2019 4 commits
  9. 12 Mar, 2019 1 commit
  10. 08 Mar, 2019 1 commit
    • Heiko Stuebner's avatar
      Fixup register handling in aarch32 reset_handler · c6c10b02
      Heiko Stuebner authored
      The BL handover interface stores the bootloader arguments in
      registers r9-r12, so when the reset_handler stores the lr pointer
      in r10 it clobers one of the arguments.
      
      Adapt to use r8 and adapt the comment about registers allowed
      to clober.
      
      I've checked aarch32 reset_handlers and none seem to use higher
      registers as far as I can tell.
      
      Fixes: a6f340fe
      
       ("Introduce the new BL handover interface")
      Cc: Soby Mathew <soby.mathew@arm.com>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      c6c10b02
  11. 05 Mar, 2019 3 commits
  12. 28 Feb, 2019 13 commits
  13. 27 Feb, 2019 4 commits
    • Varun Wadekar's avatar
      Tegra: Support for scatterfile for the BL31 image · c2ad38ce
      Varun Wadekar authored
      
      
      This patch provides support for using the scatterfile format as
      the linker script with the 'armlink' linker for Tegra platforms.
      
      In order to enable the scatterfile usage the following changes
      have been made:
      
      * provide mapping for ld.S symbols in bl_common.h
      * include bl_common.h from all the affected files
      * update the makefile rules to use the scatterfile and armlink
        to compile BL31
      * update pubsub.h to add sections to the scatterfile
      
      NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
      
      Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c2ad38ce
    • Antonio Nino Diaz's avatar
      Add support for pointer authentication · b86048c4
      Antonio Nino Diaz authored
      
      
      The previous commit added the infrastructure to load and save
      ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
      didn't actually enable pointer authentication in the firmware.
      
      This patch adds the functionality needed for platforms to provide
      authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
      enable pointer authentication in the firmware itself. This option is
      disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
      enabled.
      
      Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      b86048c4
    • Antonio Nino Diaz's avatar
      Add ARMv8.3-PAuth registers to CPU context · 5283962e
      Antonio Nino Diaz authored
      
      
      ARMv8.3-PAuth adds functionality that supports address authentication of
      the contents of a register before that register is used as the target of
      an indirect branch, or as a load.
      
      This feature is supported only in AArch64 state.
      
      This feature is mandatory in ARMv8.3 implementations.
      
      This feature adds several registers to EL1. A new option called
      CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
      them during Non-secure <-> Secure world switches. This option must be
      enabled if the hardware has the registers or the values will be leaked
      during world switches.
      
      To prevent leaks, this patch also disables pointer authentication in the
      Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
      be trapped in EL3.
      
      Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      5283962e
    • Antonio Nino Diaz's avatar
      Cleanup context handling library · 4d1ccf0e
      Antonio Nino Diaz authored
      
      
      Minor style cleanup.
      
      Change-Id: Ief19dece41a989e2e8157859a265701549f6c585
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      4d1ccf0e